MEKALA GIRISH KUMAR
@tkrcet.ac.in
Associate Professor and ECE
TKR College of Engineering and Technology
RESEARCH, TEACHING, or OTHER INTERESTS
Engineering, Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials, Engineering
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Mekala Girish Kumar, Malothu Rajeswari, Yash Agrawal, and Rajeevan Chandel
The Electrochemical Society
In this paper, signal integrity assessment is carried out for graphene nanoribbon field effect transistor (GNRFET) based ternary logic with dielectric inserted multi-layered GNR (MLGNR) interconnects. The analyses are carried out for crosstalk effects and eye diagrams with and without shielding lines. In this paper firstly, it is observed that the dielectric inserted MLGNR interconnects show better than copper (Cu) and multiwall carbon nanotube (MWCNT) interconnects. Secondly, active shield technique is adopted, and observed that it exhibits better performance than without shield and passive shield techniques. Also, the power-delay product performance parameter is evaluated and envisaged that active shield technique outperforms passive technique. Further, the eye diagram analysis is carried out for different bit rates. The different performance analyses in the paper have been carried out for 10 nm technology node.
Mekala Girish Kumar, Yash Agrawal, and Vobulapuram Ramesh Kumar
IEEE
Dielectric inserted side contact multilayer graphene nanoribbon (DSMLGNR) interconnect is envisaged as one of the prominent solutions for on-chip global interconnects. The tremendous growth in nanofabrication technology processes and huge number of transistors on a very large scale integrated (VLSI) silicon chip have made process-induced variations in devices and interconnects quite prominent. To investigate these variations a driver-interconnect-load system is considered in the present work. The impact of device and interconnect parameter variability on the electrical performance of on-chip DSMLGNR interconnect system is analyzed. The Monte Carlo analyses for propagation delay and power dissipation are performed using HSPICE simulations for DSMLGNR interconnects.
Takshashila Pathade, Yash Agrawal, Rutu Parekh, and Mekala Girish Kumar
IEEE
Rigorous technology scaling results in embedding billions of transistors and interconnects on to a VLSI chip. This leads to high speed operation and more functionality in integrated circuits (ICs). However there is trade-off between speed and power in VLSI designs. At submicron technology nodes high power consumption becomes a challenging deal. It has been observed from literature that majority of the power dissipation happens in processing elements. One such basic operational component of any processor is arithmetic logic unit (ALU). This unit is designed with the help of combinational digital circuits to perform different arithmetic and logic operations. Data registers are used to hold the operands and result of ALU operation. Hence, for low power application ICs power dissipation at ALU, data registers and interconnections between them need to be taken care. For this purpose this research work has focused on implementing a low power ALU system using graphene based device and interconnects. Carbon nanotube field effect transistors (CNTFETs) are used to design basic logic gates that reduce power consumption of the system while multiwall carbon nanotube bundle (MWCNTB) interconnects are incorporated in connection between data registers that helps to increase speed of the system. 8-bit ALU, and data registers are designed using bottom–up approach, in which each system block is implemented using basic digital circuit. For validation purpose simulated results are compared with CMOS based ALU system. Experimentation is carried out at 22nm technology node. It is speculated from this work that CNTFET are good alternative for CMOS based transistors for low power application as well as higher speed.
Mekala Girish Kumar, Yash Agrawal, Vobulapuram Ramesh Kumar, and Rajeevan Chandel
Elsevier BV
Gurijala Deepthi, Mekala Girish Kumar, and Madhavi Tatineni
The Electrochemical Society
Takshashila Pathade, Yash Agrawal, Rutu Parekh, and Mekala Girish Kumar
IEEE
Advancement in VLSI technology in nano-regime facilitates high-speed operation with allowing more functionalities in integrated circuit (IC) designs. In such nanoscale ICs, devices and on-chip interconnects play a vital role in regulating system performance such as latency and power-consumption. The present silicon (Si) field effect transistors (FETs) and copper interconnects are highly limited by several non-ideal effects which crop up significantly in the nano scaled technologies. In this direction, prominent graphene enabled carbon nanotube (CNT) has proven to be prospective alternative over both existing Si-FETs and copper interconnects. The current work eloquently incorporates both these novel emerging CNT based FET and interconnects for the driver-interconnect-load (DIL) model for IC design. Further, effective CNTFET based repeaters have been included in the DIL model for enhancing the system performance. It is investigated that CNTFET based DIL model along with repeaters significantly improves the signal latency and power-dissipation over the conventional design based on Si-FET and copper interconnects.
Takshashila Pathade, Yash Agrawal, Rutu Parekh, and Mekala Girish Kumar
Institute of Electrical and Electronics Engineers (IEEE)
The emerging VLSI technology and simultaneously highly dense packaging of devices and interconnects in nano-scale chips have prosperously enabled realization of system-on-chip designs and advanced high-performance computing applications. Concurrently, these have aggravated inevitable challenges in miniaturized integrated circuits (ICs). One of the main limiters in the performance of high-speed VLSI designs is the on-chip interconnects. The emerging graphene based mixed carbon nanotube bundle (MCNTB) interconnects have been investigated as one of the most suited and physically realizable on-chip structure. The present work focuses on utilization of MCNTB as nano-interconnects in the optimized way. Determining optimized placement of CNTs in MCNTB configuration is tedious, skilful task and meagerly explored till date. This has been innovatively taken-up in the current work. In the present paper, novel and efficient particle swarm optimization (PSO) technique is explored and innovatively incorporated to obtain optimal distribution of CNTs in a given rectangular area. The objective function considered for the design is to maximize the tube density. Several signal integrity analyses have been executed. The proposed optimized mixed CNT bundle structure is compared with other different configurations of CNT bundle structures. It is analyzed that the proposed optimized MCNTB configuration produces highly favorable results and is apt suitable for futuristic nano IC designs. The different modelling and performance analyses are performed using MATLAB, SPICE and ADS EDA tools.
Takshashila Pathade, Yash Agrawal, Rutu Parekh, and Mekala Girish Kumar
Springer Singapore
Nikita Patel, Yash Agrawal, Rutu Parekh, and Mekala Girish Kumar
IEEE
In today's modern era, zest for low power applications and miniaturized gadgets has increased tremendously. Operating devices and circuits in subthreshold region of operation is an optimum technique to attain low power requirements in the system. On-chip interconnects that connect and facilitate signal transmission between devices and different modules as well as provide power and clock connections are one of the dominating parts of system. At deep submicron technologies, interconnects majorly affect and are deciding output performance parameter. To get higher performance, copper on-chip interconnects have been replaced by next-generation graphene interconnects. At miniaturized technology nodes, variation due to temperature, fabrication process and environmental fluctuations crops up significantly that varies the system output in on-chip ICs. As a result, variability analysis of on-chip interconnects at nano regime in subthreshold region has become need of the hour. In the present paper, effective variability analysis of graphene interconnect in subthreshold region is presented for the first time to the best of the knowledge of authors. Process corner, parametric and Monte-Carlo analyses have been performed to determine variability effect in on-chip multilayer graphene nanoribbon (MLGNR) interconnects. The different variability analyses have been performed at 32nm technology node.
Yash Agrawal, Eti Maheshwari, Mekala Girish Kumar, and Rajeevan Chandel
Springer Singapore
Yash Agrawal, R. Chandel, Mekala Girish Kumar and R. Parekh
Institution of Engineering and Technology
In today's sophisticated nanoera and miniaturised densely packed integrated circuit (IC) designs, on-chip interconnects have become one of the dominant governing factors in determining the overall performance of very large scale integration (VLSI) system. In pursuit to attain high performance, to quench the thirst of continuously increasing demands of semiconductor VLSI industry and to boost up the integrated applications on the calculated limited silicon chip area, hunt for new potential and prospective design techniques have always been on priority and rigorously explored by several researchers. Current mode approach for on-chip interconnects is one of the aptly suited signalling schemes and effective performance improvement techniques for high-end IC designs. An accurate analytical model formulation of on-chip interconnects together with prospective current mode signalling (CMS) scheme and evaluating their performance are crucial and important issue. In this chapter, explicit expressions of various performance metrics for on-chip interconnects are formulated. The performance of interconnects using two varying signalling schemes namely conventional voltage and advanced current mode is investigated. The various performance metrics considered are voltage swing over interconnect line, delay, power dissipation, energy dissipation and bandwidth. It is found that voltage mode signalling (VMS) has advantage of reduced power and energy dissipation of nearly 8.6% and 9.2%, respectively, as compared to CMS scheme. It is also investigated that CMS has about 53% lesser delay and 161% higher bandwidth than VMS scheme. The effect of interconnect length and pulse period variations on the performance parameters of the interconnect using VMS and CMS schemes are also analysed. The proposed analytical model results are validated using SPICE simulation EDA tool and high level of accuracy has been realised. The present work keenly focuses on advanced current mode approach and henceforth analysing the effectiveness of different signalling schemes for high performance on-chip VLSI interconnects in ICs.
Mekala Girish Kumar, R. Dhiman, Yash Agrawal and A. Chandel
Institution of Engineering and Technology
The package of the silicon chip is an important aspect of VLSI. The package determines the size of ICs. Different IC packages allow the dies to connect with the PCB and it affects the performance of IC. These packages offer a connection with PCB, atmosphere protection and mechanical stability for the IC. The demand of improvement in IC package is increasing day by day due to the increased density of IC. The design of packages grew from through-hole to surface mount technology, from WB to flip -chip and from dual-inline packaging to chip scale packaging. Although there has been tremendous progress in this area, it is in the middle of another evolution. This progress is the evaluation of the 3D packaging design. This design provides more than 100% PE and enhances performance metrics through decreased interconnection length. This is achieved by vertical connections of stacking chips using TSVs. Vertically connected TSVs also facilitate heterogeneous integration of dies in realising on a single chip. However, the selection of filler material in TSVs plays a vital role in the reliability of 3D ICs. There are some challenges in the areas of thermal management and electrical design. In the present study, four different surrounding materials, that is, SiO2 , Si3N4 , Al203 and Hf0 2 have been considered. The equivalent stress and the resultant structure deformation of filler material (Cu and CNT) of TSVs are observed. It is noticed that the deformation in the structure of CNT-based TSVs is lesser as compared to Cu -based TSVs. Further, Hf0 2 possesses significantly lesser deformation as compared to SiO2 and Al2O3.
Harish Pulluri, N. Goutham Kumar, U. Mohan Rao, Preeti, and Mekala Girish Kumar
Springer Singapore
Yash Agrawal, M Girish, and Rajeevan Chandel
Springer Science and Business Media LLC
Yash Agrawal, Rajeevan Chandel, Mekala Girish, and Rutu Parekh
IEEE
Analytical modeling and simulative investigation are the driving thrust for the performance analysis of very large scale integrated (VLSI) circuits and systems. Contemporary and accurate analytical models are essential for comprehensively understanding the circuit behavior and development of new models. In the present work, motivationally subthreshold region of operation is investigated for on-chip system comprising of driver-interconnect-load using advanced numerical method based finite-difference timedomain (FDTD) technique for the first time. Integrated circuits operating in subthreshold region are of preeminent significance for several highly demanding portable e-gadgets in low power regime and consequently investigated in the present paper. The driver current under subthreshold region are defined by exponential current model. Practical CMOS gate has been incorporated for the accurate modeling of driver gate. Technology node considered is 22nm. It has been investigated that the proposed analytical model for subthreshold region of operation using FDTD technique is highly accurate with respect to SPICE simulation results.
Haritha Yeleti, Mekala Girish Kumar, Rajeevan Chandel, and Yash Agrawal
IEEE
In the present work, performance of normal multilayer graphene nanoribbon (NMLGNR), doped MLGNR (DMLGNR) and dielectric inserted MLGNR (DiMLGNR) are analysed using coupled line interconnect system. The transient and crosstalk analysis of NMLGNR, DMLGNR and DiMLGNR interconnects are presented. By performing transient analysis, the average propagation delay for DiMLGNR exhibits the best performance amongst the three types of interconnect-systems under consideration. The crosstalk delay of DiMLGNR interconnect is 62.7% and 25.7% lesser compared to that of NMLGNR and DMLGNR interconnects respectively.
Yash Agrawal, Mekala Girish Kumar, and Rajeevan Chandel
Springer Science and Business Media LLC
Mekala Girish Kumar, Rajeevan Chandel, and Yash Agrawal
Institute of Electrical and Electronics Engineers (IEEE)
In this paper, the crosstalk effects in coupled multiwalled carbon nanotube (MWCNT) interconnects have been analyzed. An unconditionally stable finite-difference time-domain (USFDTD) technique has been used for the crosstalk model. The in_phase delay, out_phase delay, and crosstalk noise for coupled interconnect lines have been determined. It is observed that crosstalk effect is less severe in MWCNT interconnects compared to the conventional copper interconnects. The results of the proposed model have been verified with the conventional FDTD technique, hailey simulation program with integrated circuit emphasis (HSPICE), and feature selective validation. For transient analysis, the proposed model on an average consumes 46% lesser CPU runtime as compared to the conventional FDTD technique. Further, stress and electro-migration effects have been analyzed for copper and MWCNT interconnects. The mean time to failure of MWCNT interconnects is found to be superior than that of copper interconnects.
Girish Kumar Mekala, Yash Agrawal, and Rajeevan Chandel
Institution of Engineering and Technology (IET)
In this work, performance of dielectric inserted side contact multilayer graphene nanoribbon (Di-side-GNR) coupled interconnects using unconditionally stable finite-difference time-domain (USFDTD) technique has been investigated. The model developed for the same, overcomes the limitation of Courant stability criterion prevalent in the conventional finite-difference time-domain (FDTD) technique. The proposed model accurately analyses the crosstalk effect in copper (Cu), side contact multilayer graphene nanoribbon and Di-side-GNR interconnects. It is found that the crosstalk effect is least in Di-side-GNR amongst the three types of interconnect considered in this study. The proposed model and HSPICE simulation results match closely. Further, for transient analysis USFDTD technique based proposed model takes nearly 1.5 times lesser CPU runtime compared to the conventional FDTD technique.
Yash Agrawal, Mekala Girish Kumar, and Rajeevan Chandel
Institute of Electrical and Electronics Engineers (IEEE)
A novel unified model, for conventional copper and futuristic multilayer graphene nanoribbon (MLGNR) interconnects, based on a finite-difference time-domain (FDTD) technique has been proposed in this paper. The performance of quasi-transverse electromagnetic model of interconnects has been exhaustively analyzed for both voltage-mode signaling (VMS) and current-mode signaling (CMS) schemes. The effect of variations in edge roughness and dopant dependent Fermi energy in MLGNR interconnects has been examined. The crosstalk and coupling effects in interconnects have been investigated by incorporating capacitive and inductive interconnect parasitic elements. From the results carried out for 32-nm technology node, it has been observed that for similar dimensions and operating conditions, MLGNR interconnects show a significant performance improvement over the copper interconnects. The results also show that the CMS scheme outperforms VMS scheme at global wire lengths and is very suitable for state-of-the-art chip applications. The proposed model results are in close propinquity with the SPICE results. Furthermore, the FDTD-based model is computationally efficient compared to SPICE.
Yash Agrawal, M. Girish, and Rajeevan Chandel
Springer Singapore
Mekala Girish Kumar, Yash Agrawal, and Rajeevan Chandel
Springer Singapore
Yash Agrawal, Mekala Girish Kumar, and Rajeevan Chandel
Institute of Electrical and Electronics Engineers (IEEE)
The performance of current-mode signaling (CMS) scheme in carbon nanomaterial based multiwall carbon nanotube (MWCNT) bundle on-chip interconnect using finite-difference time-domain (FDTD) technique is investigated in the present paper. A very comprehensive model that analyzes both the traditional copper and the next-generation MWCNT bundle interconnects is presented. Further, this model is applicable for both the conventional voltage-mode signaling (VMS) and the delay-efficient CMS schemes. The number of MWCNT shells in a bundle interconnect is varied, and it is analyzed that MWCNTs with larger number of shells have better performance than both MWCNTs consisting of lesser number of shells and the copper interconnects. It is analyzed that CMS scheme has superior performance than VMS scheme in terms of smaller propagation delay and reduced crosstalk-induced delay. Various analyses have been performed for 32-nm technology node and are validated using SPICE simulations. The results obtained from the proposed FDTD based model and SPICE are found to be in close agreement, and the maximum error is within 3%.
Yash Agrawal, Rajeevan Chandel, and Mekala Girish Kumar
IEEE
In nanometer regime, graphene nano-ribbon (GNR) has been identified as one of the prominent materials for on-chip interconnects. Current-mode signaling (CMS) has higher performance over conventional voltage-mode signaling (VMS) technique. VMS technique has received wide attention. However, impressive CMS technique has been less explored and needs more investigation. This paper efficiently analyzes multilayer graphene nano-ribbon (MLGNR) interconnect using current-mode signaling technique. Propagation delay, power dissipation and bandwidth are determined for CMS MLGNR interconnect. The performance of CMS MLGNR interconnect is compared with CMS copper interconnect. MLGNR interconnect is analyzed using equivalent single conductor (ESC) model and is driven by CMOS gate. It is analyzed that with increase in interconnect length, propagation delay increases while power dissipation and bandwidth decrease. The effect of variations in number of graphene layers in MLGNR interconnect is also analyzed. It is investigated that as the number of graphene layers increases, the performance of MLGNR interconnect improves. Further, the impact of variations in signal transition period is examined. The signal transition period variations severely affect the performance of the system. It is investigated that CMS MLGNR interconnect outperforms its counterpart CMS copper interconnect and is aptly suited for integrated circuit designs.
Mekala Girish Kumar, Rajeevan Chandel, and Yash Agrawal
IEEE
This paper deals with timing and stability analysis of single wall carbon nanotube (SWCNT) bundle and multiwall carbon nanotube (MWCNT) interconnects. The performance of SWCNT and MWCNT interconnects are analyzed using driver-interconnect-load system. It is analyzed that MWCNT interconnects are more stable than SWCNT bundle interconnects. It is illustrated that stability of both SWCNT bundle and MWCNT interconnects increases as the length of interconnects increase. The analytical model for stability and step response using ABCD matrix have been presented. The results are verified using SPICE simulations. The average error between analytical and simulation results is 2.1%.