Joseph S Chang
@ntu.edu.sg
Professor, School of Electrical and Electronic Engineering
Nanyang Technological University
RESEARCH INTERESTS
Electronics
Bioengineering
Acoustics
Space Electronics
Scopus Publications
Scopus Publications
Zixian Zheng, Wei Shu, and Joseph S. Chang
Institute of Electrical and Electronics Engineers (IEEE)
Junkai Zhao, Kwen-Siong Chong, Wei Shu, Mengu Cho, and Joseph S. Chang
Institute of Electrical and Electronics Engineers (IEEE)
Amitha Saleem, Amal Chandran, Sarthak Srivastava, Joji John Varghese, and Joseph S. Chang
Elsevier BV
Junkai Zhao, Kwen-Siong Chong, Wei Shu, and Joseph Chang
IEEE
Single-event-latchup (SEL) in a semiconductor device is an undesirably induced high current state, typically rendering the affected device to be non-functional and compromising its operating lifetime. The lower-current SEL phenomenon – the micro-SEL – is often difficult to detect, particularly when the normal operating current of the protected device is variable and the magnitude of micro-SEL currents is low, yet different under different operating conditions. In Machine-Learning (ML), the said variable current inadvertently affects the multiple features of the input current profile required for micro-SEL detection, thereby severely reducing the detection accuracy. In this paper, we propose a data pre-processing module to improve the accuracy of the ML-based micro-SEL detection under the aforesaid current conditions. The proposed pre-processing module encompasses the following. Prior to classification by ML, the input current profile is processed by a data pre-processing module employing a proposed background subtraction algorithm and proposed adaptive normalization algorithm. By filtering the irrelevant base current and normalizing the micro-SEL current based on the base current value, the data pre-processing module provides improved accurate features of the input current profile and widens the difference between normal samples and micro-SEL samples in the feature space. Ultimately, the proposed module facilitates ML algorithms to generate a more accurate decision boundary. The outcome is a worthy $\\sim$ 13% accuracy improvement (from $\\sim$ 79% to $\\sim$ 92%) in the micro-SEL detection in a device operating with variable currents.
Jinhen Lee, Victor Adrian, Sun-Yang Tay, Yanshan Xie, Bah-Hwee Gwee, and Joseph Chang
IEEE
The passive devices in state-of-the-art miniaturized switched-mode DC-DC converters are generally integrated by means of on-chip and in-package methods. Nevertheless, the quality is poor-to-moderate, thereby compromising the power-efficiency. In this paper, we propose the miniaturization of the DC-DC converter by means of realizing its passive devices as embedded devices that are printed within a high-density 3D inkjet printed-circuit-board (PCB). We propose a fourth-order stacked LC filter embodying passive components with small values-effectively at no additional cost because they are embedded through 3D-printing. For the inductor and capacitor, we propose to adopt a high- $Q$ solenoidal structure and the metal-insulator-metal planar structure, respectively. The proposed filter is printed within the 3D-PCB with a compact 124 mm3volume due to the stacked arrangement. The measured AC attenuation is 21.2 dB at 200 MHz. The filter is further verified by means of computer simulations of a DC-DC buck converter. Simulation results of the converter employing the filter show a low output voltage ripple at 146 mV and a high peak power-efficiency of ~78% at 200 MHz switching frequency with 150 mA load current.
Yanshan Xie, Victor Adrian, Sun-Yang Tay, Jinhen Lee, Pak Kwong Chan, and Joseph Chang
IEEE
This paper presents a digital current sensor for digitally-controlled current-ripple-based DC-DC buck converters to estimate the instantaneous inductor-current ripple accurately in both the Discontinuous (DCM) and Continuous (CCM) Current Modes. The current sensor employs a proposed dual-mode input multiplexing technique to select an appropriate representation of the pertinent voltage of the switching node $(\\boldsymbol{V}_{\\boldsymbol{x}})$ in any mode, thereby allowing the current to be estimated more accurately compared to that of the prior-art design. The accurate inductor-current ripple information enables the controller to yield output-voltage transient response with small overshoot or undershoot (OS/US) and fast settling time. Benchmarking results using a digitally-controlled current-ripple constant on-time DC-DC buck converter show that the converter employing the proposed sensor achieves $\\geq \\mathbf{49}{\\%}$ smaller OS/US and $\\geq \\mathbf{45}{\\%}$ faster settling time at the output voltage in both the DCM and the CCM collectively compared with that of the same converter but with the prior-art sensor.
Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Joseph S. Chang, and Bah-Hwee Gwee
Institute of Electrical and Electronics Engineers (IEEE)
Encryption in field-programmable gate array (FPGA) often provides a good security solution to protect data privacy in Internet-of-Things systems, but this security solution can be compromised by side-channel attacks (SCAs). In this article, we present an FPGA-based dual-hiding asynchronous-logic (async-logic) advanced encryption standard (AES) accelerator, which is highly resistant against SCAs and yet low area/energy overheads. The proposed AES accelerator achieves vertical (amplitude) SCA hiding via an area-efficient dual-rail mapping approach and a zero-value (ZV) compensated substitution-box (S-Box), while enhancing the horizontal (temporal) SCA hiding of async-logic operations via a timing-boundary-free input arrival-time randomizer and a skewed-delay controller. A comprehensive SCA evaluation is performed with 11 SCA models, and we show that our proposed design can offer a strong SCA resistance with measurement-to-disclosure (MTD) of >20 million traces. To our best knowledge, our design is the most secure AES design evaluated with the largest number of traces in FPGA. To compare the design overheads for security, we quantify the figure of merit as normalized (Area <inline-formula> <tex-math notation="LaTeX">$\\times $ </tex-math></inline-formula> Energy/MTD(All) <inline-formula> <tex-math notation="LaTeX">$\\times 10^{6}$ </tex-math></inline-formula>). The figure of merit of our proposed design is <inline-formula> <tex-math notation="LaTeX">$403\\times $ </tex-math></inline-formula> smaller than the benchmark dual-rail synchronous-logic design and <inline-formula> <tex-math notation="LaTeX">$95\\times $ </tex-math></inline-formula> smaller than a reported async-logic design.
Sun-Yang Tay, Victor Adrian, Joseph Chang, Jinhen Lee, and Bah-Hwee Gwee
IEEE
Planar air-core inductors come in a variety of geometrical shapes, including in the form of the conventional spiral geometry and novel complex geometries. In the design phase of a system, the inductance of the employed inductor would need to be ascertained. This is usually ascertained by tedious mathematical derivations on a segment-by-segment (inductor) basis or time-consuming computer modeling, and the complexity can become intractable for complex geometries. In this paper, we propose a versatile, yet accurate, vector-based method to ascertain the inductance of planar air-core inductors with virtually any geometry, including novel complex geometry inductors—rather easily. Our proposed method decomposes the inductor segments into vectors, and thereafter utilizes geometric models to compute the inductance in a systematic fashion. We benchmark our proposed method against the conventional electromagnetic field solver simulations to estimate the inductances of six planar inductors ranging from a conventional spiral air-core inductor to that embodying different and complex geometries. On the basis of these six inductor examples, we show that our method is highly accurate with a worst-case error of $\\sim 5$% compared to that obtained using conventional electromagnetic field solver. Of particular interest, our modeling for novel complex geometry planar inductors is relatively simple.
Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, and Bah-Hwee Gwee
IEEE
Differential Deep Learning Analysis (DDLA) is a deep learning-based non-profiling side-channel attack leveraging neural networks to classify Physical Leakage Information with labels. To avoid the Class Imbalance Problem (CIP) of significantly different data sizes in different data groups, DDLA employs bit labels. However, applying bit labels will be less effective for exploiting leakage. In this paper, we propose to employ Correlation optimization Deep Learning Analysis (CO-DLA) to circumvent the CIP in DDLA by converting the classification in DDLA into a correlation optimization. Bus labels can then be used to exploit stronger leakage information. To validate the attack efficacy improvement, we perform experiments on ASCAD synchronized and de-synchronized masked AES-128 datasets. For the synchronized masked dataset, our proposed CO-DLA requires only 5k traces, which is 75% lesser than the 20k traces required by the reported DDLA, to reveal the key-byte. For the 2 de-synchronized masked datasets, our proposed CO-DLA requires only 10k traces to reveal the key-byte from both of them while the reported DDLA fails to reveal the key-byte.
Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Joseph Chang, and Bah-Hwee Gwee
IEEE
We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator embodying both the masking and hiding SCA countermeasures. Our async-logic masked AES accelerator adopts a dual-rail data encoding to perform the masked 128-bit AES operations, and to enable dual-hiding to moderate both the amplitude (vertical dimension) and the time (horizontal dimension) of the side-channel signals. We implement our async-logic masked AES accelerator in FPGA and comprehensively perform the SCA evaluations based on the electromagnetic (EM) emanation. The SCA evaluations are performed based on bus-wise Hamming Distance model, bus-wise & bit-wise Hamming Weight models, and Zero-Value (ZV) model. Based on our experiment results, we show that our async-logic masked AES is secured against SCA with 1 million EM emanations. This is at least $8.3 \\times$ more resistant than synchronous-logic masked AES and $200 \\times$ more resistant than the synchronous-logic unmasked AES.
Jinhen Lee, Victor Adrian, Joseph Chang, Yin Sun, and Sun-Yang Tay
IEEE
The average power-efficiency of integrated DC- DC converters for Internet-of-Things is generally compromised over a wide load current range. This is because their efficiency is typically severely compromised at light load currents. We present a novel asymmetrical segmented power-stage configuration to improve the average power-efficiency of integrated converters. We achieve this by configuring different power-stage segments with different sizes of power transistors and their inductors, and a circuit to enable the corresponding segment for high power-efficiencies at different load conditions. Specifically, the circuit enables the segment with small-sized power transistors and a large inductor for light-load operations, and conversely, it enables the segment with large-sized power transistors and a small inductor for heavy-load operations. The integrated converter employing our proposed configuration is designed using a CMOS 180 nm process for 2. 5-3.3V input, 1.2 V output, and 50 MHz switching frequency. Simulation results show the proposed converter achieves a high average power-efficiency at ~73% over a wide load current range of 5-200mA. When benchmarked against the competing contemporary designs, the proposed converter features 5-30% higher average power-efficiency over the wide load current range, and >34% higher power-efficiency at 20 mA light load.
Yuchen He, Junkai Zhao, Juanda, Wei Shu, Kwen Siong Chong, and Joseph Chang
IEEE
As an increasing number of Commercial-Off-the-Shelf (COTS) integrated circuits are employed in space missions, radiation-induced failures become an obvious risk to these missions. Various radiation effects on COTS in space applications are reviewed and discussed. Among various radiation effects, Single Event Latchup (SEL) and Single Event Upset (SEU) are the two most critical effects severely impacting power reliability and data integrity of COTS, respectively. To protect COTS in space missions against these radiation-induced failures, a design philosophy is proposed in this paper, with the aim of fundamentally ascertaining power reliability and data integrity. The design philosophy embodies two radiation hardened products, LDAP (Latchup Detection And Protection) and Voter, which are invented and produced by Zero-Error Systems. Specifically, LDAP serves to intelligently detect the occurrence of SEL and rapidly mitigate it by power cycling, hence enhancing power reliability. Voter, on the other hand, serves as the last checkpoint of a Triple Modular Redundancy system and mitigates SEU by always outputting the correct data, hence improving data integrity. The proposed design philosophy embodying LDAP and Voter collectively and significantly enhances COTS’ reliability, desirably allowing satellite manufacturers to select and employ COTS freely.
Kwen-Siong Chong, Jun-Sheng Ng, Juncheng Chen, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Joseph Chang, and Bah-Hwee Gwee
Institute of Electrical and Electronics Engineers (IEEE)
We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow with relative timing to simplify the AES realization in Field-Programmable-Gate-Array (FPGA). Second, we optimize completion detection circuits therein to achieve a low power/overhead solution. Third, we propose a randomized delay-line control and a data-propagation control to amplify the dual-hiding SCA countermeasures for our async-logic AES accelerator. Fourth, we validate the async-logic design flow based on two commercially-available Sakura-X and Arty-A7 FPGA boards. Fifth, we comprehensively evaluate 74 SCA attacking models for our async-logic AES accelerator on these two boards, and compare the results against a benchmarking AES based on synchronous-logic (sync-logic). We show that our async-logic AES accelerator is unbreakable within 1 million electromagnetic (EM) traces where the sync-logic counterpart is breakable within < 30K EM traces. To our best knowledge, our async-logic AES accelerator is the first async-logic AES design evaluated comprehensively at the first/last round, at various attacking locations (i.e. before/after Substitute-Box), and with various Hamming weight/distance, bit model, and zero-model of SCAs.
Yong Qu, Wei Shu, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang, Yue Li, Zixian Zheng, and Joseph S. Chang
IEEE
Portable devices (e.g. smartphones) are typically equipped with Lithium (Li)-ion batteries and in-situ chargers [1],[2]. Due to the increasing demand for fast charging, the battery charger requirements are becoming stringent, demanding smooth mode transition, high power-efficiency, large output power, and small form-factor. In comparison with linear or switched capacitor topologies, an inductor-based switching charger [3],[4] – the interest of this paper – is highly desirable to offer a wide input voltage range and a flexible output current [5],[6]. However, present-art switching charger designs [3]–[6] suffer from the difficulty to meet these requirements because of their potential issues, including instability at mode transitions, excessive hard-switching power loss, single-input power rail limitation, and bulky output inductor.
Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, and Bah-Hwee Gwee
IEEE
The attack efficacy of Differential Power Analysis (DPA), a popular side channel evaluation technique for key extraction, is compromised by the false highest Difference Of Means (DOMs) value ('ghost peaks') in the DOMs matrix produced in a conventional DPA. The ghost peak is generated by the wrong key guess and always occurs in the conventional DPA when the number of side channel traces is not enough. In this paper, an improved version of the conventional DPA termed as Normalized DPA (NDPA) is proposed to circumvent the ghost peak. With the analysis on the generation of ghost peaks in the conventional DPA, we observed that by normalizing the DOMs matrix, the ghost peaks can be greatly suppressed. We model the proposed NDPA mathematically and show that it performs better than the conventional DPA. We further provide the experimental validations on a set of 200k power simulation traces on AES S- Box and 500 EM traces from ASCAD dataset. Based on the attack results of these datasets, our proposed NDPA requires (up to 68%) lesser number of traces to reveal a correct key when compared to the conventional DPA.
Yong Qu, Wei Shu, Lei Qiu, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang, and Joseph S. Chang
Institute of Electrical and Electronics Engineers (IEEE)
Present universal serial bus (USB) battery chargers often suffer from limitations to meet the increasing demand for quick charging due to compromised power efficiency and complicated hardware implementation. In this paper, we propose a charge unifiable (QU) control scheme that enables a battery charger to improve power efficiency in a low-profile hardware manner. This scheme features fully soft-switching (vis-à-vis hard switching) and single control scheme (vis-à-vis multiple) for distinct constant current (CC) and constant voltage (CV) charging modes. To the best of authors’ knowledge, the proposed QU control scheme is the first to simultaneously offer fully soft-switching, innate CC-and-CV regulation, and seamless CC-to-CV transition. To verify the proposed design, we monolithically realize a low-profile high-efficiency fast battery charger based on this scheme. The prototype embodying a tiny 470-nH output inductor supports a maximum input voltage of 16V, output voltage of 2.2-4.2 V, output current of 0.1-2 A, and peak power efficiency of 96.2%. When benchmarked against state-of-the-art counterparts, the proposed charger features at least $2.1\\times $ smaller inductor and 7.2% higher power efficiency at both the maximum and the minimum output power charging scenarios. Further, this charger is the only design that features ≥91% power efficiency in the whole load range.
Jordan B Pasternack, Matthew L Ciminero, Michael Silver, Joseph Chang, Ronald J Simon, and Kevin K Kang
Baishideng Publishing Group Inc.
BACKGROUND The care discrepancy for patients presenting to a hospital on the weekend relative to the work week is well documented. With respect to hip fractures, however, there is no consensus about the presence of a so-called “weekend effect”. This study sought to determine the effects, if any, of weekend admission on care of geriatric hip fractures admitted to a large tertiary care hospital. It was hypothesized that geriatric hip fracture patients admitted on a weekend would have longer times to medical optimization and surgery and increased complication and mortality rates relative to those admitted on a weekday. AIM To determine if weekend admission of geriatric hip fractures is associated with poor outcome measures and surgical delay. METHODS A retrospective chart review of operative geriatric hip fractures treated from 2015-2017 at a large tertiary care hospital was conducted. Two cohorts were compared: patients who arrived at the emergency department on a weekend, and those that arrived at the emergency department on a weekday. Primary outcome measures included mortality rate, complication rate, transfusion rate, and length of stay. Secondary outcome measures included time from emergency department arrival to surgery, time from emergency department arrival to medical optimization, and time from medical optimization to surgery. RESULTS There were no statistically significant differences in length of stay (P = 0.2734), transfusion rate (P = 0.9325), or mortality rate (P = 0.3460) between the weekend and weekday cohorts. Complication rate was higher in patients who presented on a weekend compared to patients who presented on a weekday (13.3% vs 8.3%; P = 0.044). Time from emergency department arrival to medical optimization (22.7 h vs 20.0 h; P = 0.0015), time from medical optimization to surgery (13.9 h vs 10.8 h; P = 0.0172), and time from emergency department arrival to surgery (42.7 h vs 32.5 h; P < 0.0001) were all significantly longer in patients who presented to the hospital on a weekend compared to patients who presented to the hospital on a weekday. CONCLUSION This study provided insight into the “weekend effect” for geriatric hip fractures and found that day of presentation has a clinically significant impact on delivered care.
Huiqiao He, Tong Ge, Yang Kang, Linfei Guo, and Joseph S. Chang
Institute of Electrical and Electronics Engineers (IEEE)
The envelope tracking (ET) design methodology is routinely adopted to improve the efficiency of radio frequency power amplifiers (PAs). One shortcoming of state-of-the-art ET PAs is that their supply modulators are usually designed and optimized for a single communications standard. They are either incompatible in modern communication devices where multiple communications standards are used, and/or the efficiency unoptimized when the devices operate in standards other than the designed standard. To circumvent this shortcoming, a novel supply modulator for multistandard communications is proposed. The proposed design embodies a proposed dual-mode Sigma–Delta control block and an adaptive biasing Class AB amplifier, which allows the supply modulator self-adjusting its operation and optimizing the efficiency according to the application. A prototype supply modulator IC is designed and fabricated using a 180 nm CMOS process. Based on measurements, the proposed supply modulator features the highest static efficiency of 91% and the highest 3 dB backoff static and dynamic efficiency compared to the state-of-the-art supply modulators. When tracking 40 MHz LTE-A envelope signals, the prototype supply modulator achieves a high efficiency of 85% at 1.8 W output power, and the efficiency remains high >80% for a wide range of output power, from 0.5 to 1.8 W.
Joseph Chang, Tong Ge, and Tong Lin
IEEE
Contemporary digital circuits are synchronous-logic and are operationally error-free because they are designed to complete their operation within a predefined time period. In some applications, such as the MOST operating in ultra-deep subthreshold or in flexible electronics where the TFT is printed, the ensuing operation of digital circuits is prone to error. This is because the variations of the delay of the transistor are very high and the ensuing predefined time period is difficult to ascertain. In the case of the printed TFT where its substrate is flexible and hence possibly bent, the delay is possibly intractable, in part because the profile of the bending may not be known. In this paper, we will discuss the commonality between ultra-deep subthreshold and printed TFTs in terms of their variations. We describe the application of the esoteric asynchronous-logic Quasi-Delay-Insensitive (QDI) signaling protocol to design digital circuits that innately accommodate intractable delay characteristics, i.e., error-free operation despite intractable variations. To mitigate the hardware, power and timing overheads of QDI, we will present our proposed modified signaling protocol named Pseudo-QDI and our proposed Pre-Charged-Static-Logic design style.
Joseph Chang, Tong Ge, and Tong Lin
IEEE
The low carrier mobility of (printed) semiconductors and high variations of the printed/flexible electronic elements are some of the most difficult challenges for the practical realization of complex printed/flexible electronic circuits. Although contemporary circuit designs accommodate some degree of process variations in conventional silicon processes largely by negative feedback, negative feedback is largely inapplicable in printed/flexible electronics. This is because the gain of the transistors is too low in electronic circuits to realize high open-loop gain, but also because negative feedback is inapplicable to digital circuits in the traditional sense. In this paper, we describe the co-design between the first three supply chains of Printed/Flexible Electronics – the co-design between our modified semiconductor, Fully-Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics printing process and a process-variation-tolerant digital circuit design methodology. The first two co-design supply chains pertain to a low-cost screen-printing process while the last co-design chain pertains to the Quasi-Delay-Insensitive asynchronous-logic digital design methodology (vis-à-vis synchronous-logic) that is self-timed, hence virtually tolerant to any variations. We will also delineate our measurements on digital circuit based on codesign of the aforesaid supply chains, depicting the merits of our modified semiconductor, low-variation printing process, and the ensuing functional printed digital circuit.
Yong Qu, Wei Shu, and Joseph S. Chang
Institute of Electrical and Electronics Engineers (IEEE)
The power efficiency and weight of present point-of-load (POL) dc–dc converters for drone applications are often compromised because they suffer from large switching losses at continuous conduction mode for heavy loads and excessive hardware overheads at discontinuous conduction mode for light loads. This paper presents a boundary conduction mode (BCM) control scheme for POL converters embodying a single operation mode. This is achieved by means of a hysteresis voltage controller to turn on/off the output power stage when necessary. The proposed BCM control scheme achieves high power efficiency (≥91.2%) over a wide load range (5 mA–1 A) by means of fully soft switching. Specifically, a hysteretic current controller is proposed to realize ZCS, and an adaptive dead time controller is proposed to realize ZVS. Further, the proposed BCM control scheme requires a small output inductor (0.82 μH) by means of designing the customizable peak inductor current. To verify the proposed BCM control scheme, we realize a BCM-based POL converter that features an input voltage range of 5–16 V, output voltage range of 2.5–8 V, switching frequency of 1.5 MHz, peak power efficiency of 96.8%, and ≤35 mV output voltage undershoot/overshoot for 1-A load step. When being benchmarked against state-of-the-art counterparts, the proposed design features the lowest voltage undershoot/overshoot, the highest switching frequency, ∼5.7× smaller inductor, and ∼11% higher power efficiency at light loads.
Kwen-Siong Chong, Tong Lin, Weng-Geng Ho, Bah-Hwee Gwee, and Joseph S. Chang
Institution of Engineering and Technology
We have presented the appropriateness of the QDI (and pseudo-QDI) asynchronous -logic design approach to realize circuits and systems suitable for full -range DVS (from the nominal voltage near- V t voltage sub- V t voltage regions). Both block -level and gate -level pipeline structures have been presented. Using the block -level pipeline structure, we have presented an SSAVS system embodying block -level QDI asynchronous pipelines for a WSN with the objective of lowest possible power operation for the prevailing throughput and circuit conditions-V DD adjusted to within 50 mV of the minimum voltage, yet high operational robustness with minimal overheads. High robustness has been achieved by adopting the asynchronous QDI protocols, and the embodiment of our proposed PCSL. A reduced -overhead design has further been shown by adopting the asynchronous pseudo-QDI protocols, and the embodiment of PCSL. Using the gate -level pipeline structure, we have presented our proposed SABB cell design approach and evaluated an asynchronous QDI KS pipeline adder embodying SABB for full -range DVS operation. In summary, we show that QDI (and pseudo-QDI) asynchronous -logic, coupled with either PCSL or SABB cell design approaches, provides a low-cost high -reliability solution for circuits and systems exclusively designed for error free DVS.
Jordan B. Pasternack, Matthew L. Ciminero, Michael Silver, Joseph Chang, Piyush Gupta, and Kevin K. Kang
SAGE Publications
Introduction: With respect to care setting, there are mixed results in the literature with respect to the role of trauma centers in management of isolated geriatric hip fractures. During a transition from a Level 3 to a Level 1 trauma center, significant protocol changes were implemented that sought to standardize and improve the care of hip fracture patients. The objective of this study was to determine the effects of this transition on the management, efficiency, morbidity, mortality, and discharge of geriatric hip fracture patients. Methods: A retrospective chart review of geriatric hip fractures treated operatively was conducted. Two cohorts were compared: hip fractures in the year prior to (2015) and year following (2017) Level 1 Trauma designation. Primary outcome measures were length of stay (LOS), transfusion rate, complication rate, and mortality rate. Secondary outcome measures were time from emergency department (ED) arrival to medical optimization, time from medical optimization to surgery, time from ED arrival to surgery, and discharge destination. Results: There were no differences in LOS, transfusion rate, or complication rate between the two cohorts. There was a nonsignificant trend toward lower in-hospital mortality after the transition (2.24% vs 0.83%). There were no differences in time from ED arrival to medical optimization, time from medical optimization to surgery, time from ED arrival to surgery, and percentage of patients discharged home between the cohorts. Discussion: Management of operative geriatric hip fractures at our institution has remained consistent following transition to a Level 1 trauma center. There was a trend toward lower mortality after transition, but this difference was not statistically significant. We attribute the variety of findings in the literature with respect to trauma center management of hip fractures to individualized institutional trauma protocols as well as the diverse patient populations these centers serve.