Electronics
Bioengineering
Acoustics
Space Electronics
221
Scopus Publications
Scopus Publications
A Novel Quadrature-Phase Sampling Technique for Filterless, Low-Complexity, High-Alias-Suppression in VCO-ADCs Jinhen Lee, Victor Adrian, Joseph S. Chang IEEE Open Journal of Circuits and Systems, 2026 Next-generation LiDAR systems demand unprecedented resolution, requiring wide signal bandwidth and high-density pixel arrays that constrain each pixel circuit to <inline-formula> <tex-math notation="LaTeX">$\leq 0.01$ </tex-math></inline-formula> mm2. This limits the complexity and power available for anti-aliasing filtering in the receiver front-end, even though strong attenuation of interference and alias noise is critical to preserve signal fidelity. Voltage-controlled oscillator (VCO)-based analog-to-digital converters (ADCs) offer inherent anti-aliasing through spectral shaping, but for bandwidths <inline-formula> <tex-math notation="LaTeX">$\geq $ </tex-math></inline-formula>50 MHz, the attenuation is insufficient, necessitating dedicated analog filters that undermine area and power. To resolve this, we propose a novel sampling technique for VCO-ADCs, employing quadrature clocks instead of conventional clocking. The resulting output spectrum exhibits a quasi-<inline-formula> <tex-math notation="LaTeX">$sinc^{3}$ </tex-math></inline-formula>-shaped response that improves alias attenuation by ~10 dB to 80 dB at 50 MHz bandwidth—the highest reported to date—eliminating the need for analog filters. We derive an analytical expression for this response, accounting for non-idealities and offering insight into the parameters governing the shaping behavior. The technique is demonstrated with a proposed filterless, low-complexity VCO-ADC circuit in CMOS 65 nm, occupying just 0.0017 mm2—43% smaller than the state-of-the-art—and dissipating only 0.42 mW at 2 GHz sampling in simulation. Benchmarking shows a figure-of-merit of 56 fJ/conversion-step, <inline-formula> <tex-math notation="LaTeX">$\sim 1.1\times $ </tex-math></inline-formula> better than the best reported design.
An Adaptive Pre-Processing Module for ML/AI-Based SEL/μ-SEL Detection in COTS Systems without Physical Modification to the COTS System Junkai Zhao, Kwen-Siong Chong, Wei Shu, Joseph S. Chang IEEE Transactions on Nuclear Science, 2026 In our envisioned “Chang’s Next Paradigm of New Space”, COTS systems – embodying multiple COTS ICs – would be employed in space missions. When applied to COTS systems with power management ICs (including multiple voltage regulators), reported ML/AI-based SEL/μ-SEL detection approaches require access to the internal sub-power rails (after regulators). This is because regulator-induced distortions significantly obscure SEL/μ-SEL characteristics on the external power rail (before regulators). However, accessing internal rails requires physical modification, which is highly undesirable. In this paper, we propose an adaptive pre-processing module that, for the first time, enables ML/AI-based SEL/μ-SEL detection in COTS systems without physical modification. Specifically, by compensating for regulator-induced distortions, our proposed module allows ML/AI-based approaches to detect SELs/μ-SELs by monitoring only the external power rail, thereby, very advantageously, without any physical modification to the COTS system. Integrated with this proposed module, our previous reported AI-based approach achieves a high average detection accuracy of 91.1%. This is a very worthy improvement of 11.1%–53.9% over reported approaches without our proposed module, while incurring modest hardware overhead.
A High-Efficiency Fast-Transient Double Hysteretic Control Point-of-Load Converter Yuchen He, Yue Li, Wei Shu, Joseph S. Chang IEEE Transactions on Power Electronics, 2026 As portable devices become increasingly sophisticated, the demands for their power management in terms of high power-efficiency and fast-transients are congruously higher. We present herein a Point-of-Load converter (PoL) with two interesting features. One, compared to state-of-the-art PoLs with comparable transient performance, it features higher power-efficiency across most of the load range. Two, compared to state-of-the-art PoLs with similar power-efficiency, it features faster transients. These attractive features are achieved by our novel proposed Double Hysteretic Control that integrates a Voltage-Mode Hysteretic Controller (VMHC) and a CurrentMode Hysteretic Controller (CMHC). The modus operandi of the VMHC operates its Discontinuous-Conduction-Mode and Continuous-Conduction-Mode without a mode-selection circuit to derive high power-efficiency. The CMHC combines two conventional current-mode controls to prolong on-time and offtime extensions, enabling fast transients. On the basis of measurements on a monolithic prototype, the power-efficiency is >90% across the 2mA-3A load range with a peak-efficiency of 96.1%. The voltage undershoot and overshoot are 70mV and 40mV with recovery times of 3μs and 2μs in response to 2.7A step-up and step-down load current transients (1A/μs slew-rate), respectively. Compared to state-of-the-art designs, our PoL optimizes both power-efficiency and transient response, features the best Figures of Merit and is highly competitive.
Single-Ended/Differential Wideband Track-and-Hold Amplifier in 22-nm FD-SOI CMOS Process Zixian Zheng, Wei Shu, Joseph S. Chang IEEE Transactions on Very Large Scale Integration VLSI Systems, 2025 The impending 6G communication based on the software defined radio (SDR) requires a radio frequency (RF) track-and-hold amplifier (THA). This THA serves as the frequency down-converter and the single-to-differential interface to the downstream analog-to-digital converter (ADC). We present a CMOS RF THA that features wide and width (18 GHz), yet high linearity (spurious free dynamic range (SFDR) of 56.7 dB) and not requiring an external balun. These features are derived from our proposed isolation technique based on our proposed double source follower enhanced (DSFE) structure. To realize the single-to-differential conversion without an external balun, we design an independent balun as the first stage. Thereafter, we employ our proposed feedforward compensation technique (FCT) along with the reported phase correction technique (PCT) to reduce the output mismatches while simultaneously enhancing the linearity and bandwidth. We monolithically realize the RF THA in 22-nm fully-depleted silicon-on-insulator (FD-SOI) CMOS operating at 1.8 V. Measurements depict that the input bandwidth is wide (18 GHz), yet featuring high linearity (SFDR =56.7 dB at 15 GHz) with 2 GS/s sampling rate. The power consumption and the chip area are low and small at 216 mW and 0.07 mm2, respectively. When benchmarked against reported III/V RF THAs, the proposed CMOS RF THA is very competitive—comparable bandwidth, yet simultaneously higher linearity, potentially lower cost, lower power dissipation, and smaller die area. Further because it is realized in CMOS, it facilitates integration to other CMOS circuits in the same system-on-chip (SoC).
A 50-MHz Pulse-Width Modulator Embodying Low-Loss Quasi-Dynamic Comparators for Very High-Frequency DC–DC Converters Sun-Yang Tay, Victor Adrian, Joseph S. Chang IEEE Journal of Solid State Circuits, 2025 In the next-generation Internet of Things (NG-IoT) applications with sub-50-mA loads, the state-of-the-art very high switching frequencies (VHFs, e.g., 50 MHz) dc–dc converters are typically power-inefficient at light loads, e.g., 60%. This is largely due to the high power losses of high-speed static comparators employed in the pulse-width modulator of the VHF converter, e.g., ~40% of the overall power losses. Dynamic comparators may mitigate the high loss, but they are impractical to pulse-width-modulation-based converters due to the high-speed clock generator requirement. To mitigate the power losses, we present a pulse-width-modulator converter embodying a proposed quasi-dynamic (QD) comparator (and its hysteretic variant). The innovation is the first-ever comparator that features a clock-free regenerative latch (CFRL), thereby enabling the comparator to simultaneously feature the high-speed and low-loss advantages of dynamic comparators, yet clockless operation of static comparators. Our 50-MHz pulse-modulator converter, realized in 65-nm CMOS and embodying the proposed QD comparators, features a high ~82% power efficiency at 10 mA (20% of max load)—<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\ge$</tex-math></inline-formula>20% higher power efficiency than the state-of-the-art VHF converters. The proposed QD comparator therein dissipates ~145-μW power and features 2.9-ns propagation delay—<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\ge$</tex-math></inline-formula>40% lesser power-delay product than the state-of-the-art static comparators. The proposed QD comparator can be advantageously applied to replace static comparators in a myriad of applications, potentially improving their power efficiency without compromising high-speed operation.
Detection and Protection of a COTS System Against Micro-Single-Event-Latchups (μ-SELs) and SELs: A Step Toward the Next-Paradigm in New Space Junkai Zhao, Kwen-Siong Chong, Wei Shu, Joseph S. Chang IEEE Transactions on Nuclear Science, 2025 We envision that the “next-paradigm” of New Space will involve the employment of commercial-off-the-shelf (COTS) systems (embodying multiple COTS ICs) vis-à-vis individual COTS ICs today. Most COTS ICs and COTS systems are susceptible to radiation effects, where micro-single-event-latchups (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-SELs) and single-event-latchups (SELs) are of the most concern. Since reported approaches are limited to protecting an individual COTS IC, their application to every COTS IC within the system would render considerable overheads and potentially degraded performance. In this article, we propose an approach to detect and protect a COTS system (vis-à-vis an individual COTS IC) against <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-SELs/SELs, making a step toward our envisioned “next-paradigm” of New Space. Our proposed approach monitors only the current of the COTS system’s total power rail, where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-SELs/SELs may occur in any COTS IC therein. Of note, as this current is obtained outside of the COTS system, the COTS system is unmodified. We propose to adopt the long short-term memory (LSTM) neural network for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-SEL/SEL detection. Our proposed artificial intelligence (AI)-based approach achieves high (~95%) detection accuracy with fast (~0.5 ms) response time and low (~73 mW) power dissipation. Specifically, our approach improves accuracy by ~15%–60% over reported approaches and matches our prior work on an individual COTS IC (not a COTS system). It reduces power dissipation by ~11%–64% compared to reported approaches and is ~25%–55% higher than our prior work; its response time is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.6\times $ </tex-math></inline-formula>–<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$255.6\times $ </tex-math></inline-formula> faster than reported approaches and is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.2\times $ </tex-math></inline-formula>–<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.4\times $ </tex-math></inline-formula> slower than our prior work. In view of these attributes, our proposed AI-based approach is appropriate for the “next-paradigm” of New Space.
A Novel High-Accuracy Inductor-Current Estimator for Digitally-Controlled Synchronous DC-DC Buck Converters Yanshan Xie, Victor Adrian, Jinhen Lee, Joseph S. Chang Proceedings IEEE International Symposium on Circuits and Systems, 2025 This paper presents a novel digital inductor-current estimator for digitally-controlled current-ripple-based synchronous DC-DC buck converters. The estimator features high accuracy, which is imperative for current-ripple control that requires precise estimation of instantaneous DC and inductor ripple currents in both the discontinuous and continuous conduction modes. The estimation method indirectly determines the currents by constructing a digital representation of the voltage across the inductor, rendering it applicable in both conduction modes. This method is more accurate and simpler than conventional methods that estimate DC and inductor ripple currents directly in each conduction mode. Compared to state-of-the-art methods, the proposed estimator achieves an average DC current estimation error that is ≥5.7× smaller and an inductor ripple current estimation error that is ≤ 1.90% over various load conditions.
A Novel Energy-Efficient Continuous-Time Hysteretic VCO-Based Comparator Jinhen Lee, Victor Adrian, Kinglouis Steven Tantra, Bah-Hwee Gwee, Joseph S. Chang Proceedings IEEE International Symposium on Circuits and Systems, 2025 Voltage-controlled oscillator (VCO)-based comparators offer higher energy efficiency as the difference in input magnitudes increase, such as in level-crossing ADCs. Nevertheless, to date, they require a clock signal to perform comparison operations. This is incongruous with continuous-time applications, where inputs are compared continuously. Further, they lack hysteresis, a crucial feature for mitigating spurious switching that compromises energy efficiency. In this paper, we present a novel VCO-based comparator that, for the first time, simultaneously achieves continuous-time operation and high energy efficiency. The former feature is enabled by a novel continuous-time decision circuit, while the latter is achieved through a novel switched-current hysteresis circuit that mitigates spurious switching. The proposed comparator is designed in 65 nm CMOS. Simulation results show that it achieves low energy per comparison, ranging from 0.07 to 4 pJ, with an average propagation delay of ~15 ns. The average energy consumption is 0.19 pJ — ~1.8× lower than the state-of-the-art VCO-based comparator.
An Adaptive AI-based Approach to Detect and Protect COTS Systems against Micro-Single-Event-Latchups (μ-SELs) and SELs Junkai Zhao, Yin Sun, Tony Zhang, Kwen-Siong Chong, Wei Shu, Joseph S. Chang Proceedings IEEE International Symposium on Circuits and Systems, 2025 In our envisioned ‘Next Paradigm’ of ‘New Space’, commercial-off-the-shelf (COTS) systems (embodying multiple COTS ICs) would be employed as payloads in space missions. Most COTS ICs are susceptible to radiation effects, particularly Micro-Single-Event-Latchups (μ-SELs) and SELs, and their characteristics are expectedly different. Consequently, hitherto reported detection approaches require characterization of the individual COTS ICs and the entire system, thereby rendering excessive overheads when applied to different COTS systems. In this paper, we propose, for the first time, the design and implementation of an adaptive AI-based approach to detect and protect various uncharacterized COTS systems (vis-à-vis pre-characterized ones) against μ-SELs and SELs. Our proposal involves the adoption of the Long-Short-Term-Memory (LSTM) neural network with our proposed two-stage training process – ex-situ pre-training and in-situ re-training – to improve general applicability. Our FPGA-based prototype achieves high (~90%) average accuracy for four different payloads. This is a worthy improvement of 13.3%-28.5% over reported approaches, yet requiring low (~115 mW) power consumption. Collectively, our proposed approach is appropriate for resource-constrained space applications and our ‘Next Paradigm’ of ‘New Space’.
Normalized differential power analysis - For ghost peaks mitigation Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee Proceedings IEEE International Symposium on Circuits and Systems, 2021
Radiation-hardened-by-design (RHBD) digital design approaches: A case study on an 8051 microcontroller Proceedings IEEE International Symposium on Circuits and Systems, 2020
A DPA-resistant asynchronous-logic NoC router with dual-supply-voltage-scaling for multicore cryptographic applications Proceedings IEEE International Symposium on Circuits and Systems, 2020
A review of audio Class D amplifiers Yang Kang, Tong Ge, Huiqiao He, Joseph S. Chang 2016 International Symposium on Integrated Circuits Isic 2016, 2017
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications Proceedings of the 2016 Design Automation and Test in Europe Conference and Exhibition Date 2016, 2016
Fully-additive printed RFID on a plastic film Joseph Chang, Ge Tong, Lin Tong 2013 IEEE MTT S International Microwave Workshop Series on RF and Wireless Technologies for Biomedical and Healthcare Applications Imws Bio 2013 Proceedings, 2013
Catch the wave--nanotechnology, the future is now. IEEE Engineering in Medicine and Biology Magazine the Quarterly Magazine of the Engineering in Medicine Biology Society, 2010
Modeling and analysis of PSRR in analog PWM Class D amplifiers Proceedings IEEE International Symposium on Circuits and Systems, 2006
Fourier series analysis of the nonlinearities in analog closed-loop PWM class D amplifiers Proceedings IEEE International Symposium on Circuits and Systems, 2006
Optimized algorithm for computing invariants of ordinary petri nets Chong-Fatt Law, B. Gwee, J.S. Chang Proceedings 5th IEEE Acis Int Conf on Comput and Info Sci Icis 2006 in Conjunction with 1st IEEE Acis Int Workshop Component Based Software Eng Softw Archi and Reuse Comsar 2006, 2006
A low-voltage low power accumulator 10th International Symposium on Integrated Circuits Devices and Systems Isic 2004 Integrated Systems on Silicon Proceedings, 2004
A low power low voltage bang-bang control class D amplifier 10th International Symposium on Integrated Circuits Devices and Systems Isic 2004 Integrated Systems on Silicon Proceedings, 2004
A low power low voltage analog class D amplifier based on second-order sigma-delta modulator 10th International Symposium on Integrated Circuits Devices and Systems Isic 2004 Integrated Systems on Silicon Proceedings, 2004
A robust low voltage low energy asynchronous carry-completion sensing adder for biomedical applications 2004 IEEE International Workshop on Biomedical Circuits and Systems, 2004
A low power low voltage class D Amp based on sigma-delta and Bang-Bang Control 2004 IEEE International Workshop on Biomedical Circuits and Systems, 2004
A low power 16-bit booth Leapfrog array multiplier using dynamic adders Proceedings IEEE International Symposium on Circuits and Systems, 2004
A novel combined first and second order lagrange interpolation sampling process for a digital Class D amplifier Proceedings IEEE International Symposium on Circuits and Systems, 2004
A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File Proceedings of the International Conference on VLSI, 2003
A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter Proceedings IEEE International Symposium on Circuits and Systems, 2003
A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers Proceedings IEEE International Symposium on Circuits and Systems, 2003
A process- and temperature-independent inverter-comparator for pulse width modulation applications Analog Integrated Circuits and Signal Processing, 2001
A digital class D amplifier design embodying a novel sampling process and pulse generator Materials Research Society Symposium Proceedings, 2001
A novel pulse width modulation sampling process for low power, low distortion digital class D amplifiers Midwest Symposium on Circuits and Systems, 2000
Novel self-tuning pulse width modulator based on master-slave architecture for a class d amplifier Proceedings IEEE International Symposium on Circuits and Systems, 1999
Analysis and two proposed design methodologies for optimizing power efficiency of a Class D amplifier output stage Proceedings IEEE International Symposium on Circuits and Systems, 1998
Novel self-error correction Pulse Width Modulator for a Class D amplifier for hearing instruments Proceedings IEEE International Symposium on Circuits and Systems, 1998
A micropower 3V programmable highpass filter for hearing aids International Symposium on IC Technology Systems and Applications, 1997
3 V micropower programmable gm-C filter set for hearing aids Proceedings of the IEEE International Symposium on Consumer Electronics ISCE, 1997
Low power time-multiplexed SC speech spectrum analyzer undefined, 1989
Two speech processing schemes for the University of Melbourne multi-channel Cochlear implant prosthesis Proceedings IEEE International Symposium on Circuits and Systems, 1989
Switched capacitor time-division-multiplexed pole sharing technique for linear phase bandpass filterbanks Proceedings IEEE International Symposium on Circuits and Systems, 1988
