Dr. Shyam Akashe is a professor in Electronics & Communication Engineering Department and Dean International Cooperation & Projects at ITM University Gwalior. He received M.Tech degree in Electronics & Communication Engineering from Rajiv Gandhi Proudyogiki Vishwavidyalaya (RGPV), Bhopal in 2006 and Ph.D. Thapar University, Patiala (previously Thapar Institute of Engineering and Technology), Punjab in 2013. During his Ph. D. studies, he worked on Low power memory cell design.
After joining ITM University Gwalior in 2012, he leads as an M.Tech VLSI Design coordinator, focusing on low power VLSI design, modeling, FinFET based memory design, circuits for future VLSI technology, digital design and FPGA implementation. This has resulted in over 300 peer-reviewed journal and conference papers and holds more than 10 patents.
Dr. Akashe received the NSC-2005 at IIT Bombay best research paper award and his Biographical profile published in Marquis’s Who’s Who in Engineering Field, USA awarded b
EDUCATION
Ph.D. in Electronics & Communication Eng. Thapar University, Patiala, Punjab, India, 2013.
M.Tech. in Electronics & Communication Eng. Institute of Technology & Management, Gwalior, (M.P.), India, 2006.
RESEARCH INTERESTS
Low Power VLSI Design,SRAM,FPGA
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Scopus Publications
Scopus Publications
Investigating non-volatile memory architectures for neuromorphic systems with CMOS spike-timed synaptic plasticity Joshika Sharma, Shyam Akashe, Govind Murari Upadhyay Discover Computing, 2026 Learning is crucial for the brain’s ability to adapt to changing conditions. We suggest a collection of novel neuromorphic construction circuits, adjustable synapse circuits, and CMOS Spike Based Driven Synaptic Plasticity (CSBDSP) erudition algorithm devices during an attempt to generate compressed and physiologically realistic SCNNs even as limiting power Dissipation. We make two contributions to the learning rule implementation for large-scale extended neuromorphic systems. A novel OxRAM-based Non-Volatile CMOS SRAM (NVSRAM) device is introduced in this article. The 9T-SRAM architecture, especially with the integration of Ox-RAM (Oxide Resistive RAM) technology, presents improvements compared to conventional 6T SRAM and other SRAM types by enhancing stability, minimizing leakage current, and optimizing read/write performance. Comparing SRAM and NVSRAM’s performance at the memory and cell levels is advised. DG FINFET (Double gate Fin Shaped Field Effect Transistor) approaches have been used to lower the SRAM cell’s power consumption. According to the findings, the SRAM cell based on DG FINFETs performs the best in form of power Dissipation. Design impenetrability, leakage current, and power consumption are amongst the many factors that are compared. The circuits under description are constructed at 180 nm and 90 nm using high voltage CMOS technology.
A computationally efficient approach to quantum state reconstruction using robust classical shadows Sanjay Sharma, Shyam Akashe, Govind Murari Upadhyay, Amanjot Kaur Lamba Scientific Reports, 2026 Quantum state tomography is a fundamental technique for characterizing quantum systems, but its scalability remains a significant challenge. This paper investigates an efficient alternative using classical shadows to reconstruct a Bell state with high fidelity. Classical shadows provide a compressed representation of a quantum state using randomized measurements, reducing the measurement complexity compared to full quantum tomography when full state reconstruction is not required. We employed a quantum circuit to generate a Bell state and utilize 1000 snapshots to construct its classical shadow. The reconstructed density matrix is evaluated using fidelity and norm difference metrics against the ideal Bell state. Our analysis demonstrates that as the number of snapshots increases, the fidelity of reconstruction stabilizes around 0.98-1.0, with the norm difference decreasing accordingly. The results also confirm the convergence of reconstructed states towards the ideal Bell state, highlighting the efficiency and accuracy of classical shadows in quantum state estimation. Shallow shadow tomography uses shallow random circuits to estimate global quantum state properties on noisy hardware. By combining low-depth entangling gates with randomized measurements and noise-aware postprocessing, it reduces sample complexity compared to Pauli shadows while remaining experimentally feasible. Recent experiments on superconducting processors confirmed up to fivefold measurement savings.
Optimized duo directed LSTM for efficient object detection on resource constrained edge devices Shraddha S. More, Rajesh Bansode, Govind Murari Upadhyay, Shyam Akashe Discover Internet of Things, 2026 Several fields most notably object identification, have effectively employed artificial intelligence (AI). Nevertheless, deep learning (DL) models are costly in terms of memory and computational power, making it difficult to apply them in systems that must react quickly to disruptions or have restricted resources. Consequently, in implementing these deep models on edge devices lacking appreciably compromising their performance, they must be expedited and compacted to lower dimensions. In this manuscript, novel compression approaches of the DL technique are investigated and compared based on the pruning, quantization, and knowledge distillation (KD) models, an efficaciously developing method in this field. Initially, the images collected from the raw database are denoised using the Extended Kuan filtering (Ex-KF) technique to achieve better detection performance. Then, the convoluted-duo-directed long short-term memory (Conv-DDLSTM) model is introduced, and various compression processes are applied to minimize model complexities. Moreover, the proposed framework is deployed on edge mobile devices for automatic object detection (OD). The experimentation is tested with the Python Platform and a freely accessible COCO-2017 database is utilized. Various assessment measures like accuracy, F-measure, Matthew’s Correlation Coefficient (MCC), positive predictive value (PPV), Intersection of Union (IoU), mean average precision (mAP), power and memory consumption, model size, and latency are scrutinized with other conventional frameworks. The proposed method achieved overall accuracy of 98.68% and 97.93%, and power consumption of 216.70 MW and 163.25 MW for the presence and absence of compression respectively.
Energy-Efficient Neuromorphic Architectures Enabled by Resistive Memory Joshika Sharma, Shyam Akashe Journal of Trends in Computer Science and Smart Technology, 2025 Their excellent performance and compatibility with CMOS technology, while the OXRAM (Oxide-based CMOS Resistive Random Access Memory) technique used in CMOS transistors presents challenges in terms of device unpredictability and scalability, also offers potential advantages such as higher endurance, lower power consumption, and quicker reading and writing operation speeds when compared to traditional Flash memory. The inability of conventional SRAMs to store data after powering off limits their use in battery-operated mobile devices and other applications where non-volatility related to zero leakage currents is required. In the article, a new OXRAM-based Non-Volatile SRAM (NVSRAM) device is presented. It is suggested to compare the performance of SRAM with NVSRAM at the memory and cell levels. Learning is crucial for the brain's ability to adapt to changing conditions. A synaptic connection table in an external memory at a local routing node is used to learn a rule in the address domain for neuromorphic architecture. A number of parameters are compared, including design complexity, leakage current values (SRAM cells are 3.4µA, 7.4nA) and (NVSRAM-based OXRAM are 2.7 µA, 5.9nA) at 180nm and 90nm, and energy saving or power usage values (SRAM cells cell are 5.5 µA, 10.5nA) and (NVSRAM based OXRAM are 4.9 µA, 9.8nA) at 180nm and 90nm. The circuits that are being described can be realized using far-above ground voltage CMOS Cadence tools at 180 nm and 90 nm.
Memristor loaded cross-coupled differential voltage sense amplifier design with improved performance Peter Bukelani Musiiwa, Shyam Akashe, Govind Murari Upadhyay, Sanjay Sharma Scientific Reports, 2025 Sense amplifiers have of late become an important class of circuits due the major role they play in the design of low voltage memory design. It is an active circuit capable to enhance signal promulgation from the selected cell in a memory array to peripheral logic circuits and changes the random logic levels on a bit-line to the digital logic levels of the Boolean circuits in the periphery. In this paper the memristor loaded cross-coupled differential voltage sense amplifier is proposed as a possible surrogate for CMOS based cross coupled differential amplifier to reduce the area size, increase the gain and the speed of operation. With the exponential increase in the memory array sizes the bit line capacitance and cell-access resistance has become very large and this merger conjoined with the further reduction in output energy produced by the cell during reading will aggregate in the generation of a small signals from each selected cell. These small signals will make it difficult for data value detection and determination and will cause a prolonged latency times. To enhance performance speed and to provide signals that can be properly read as logic 0/1 many sense amplifiers have been designed to give faster sensing by responding to low voltage swings. To improve the gain of the sense amplifier by increasing the load resistance the memristor cells is in cooperated in amplifier. The memristor was selected as it propound reduced leakage current, populate less space area and because of quantization of conductance using memristive state allows for easy adjustability of the sense amplifier. The proposed memristor loaded sense amplifier was compared to the conventional CMOS based cross-coupled sense amplifier.
Customized Vision ARM for Segregation of Packages with Smart Picking Gauri Borkhade, Yashashvi Devadiga, Shivam Devhare, Somnath Dey, Sakshi Gharat, Shyam Akashe Proceedings 2024 6th International Conference on Computational Intelligence and Communication Technologies Ccict 2024, 2024
Power efficient shift register using FinFET technology Harshit Singh, M. Meenalakshmi, Shyam Akashe International Conference on Emerging Trends in Electrical Electronics and Sustainable Energy Systems Iceteeses 2016, 2016
Analysis of low power reduction in voltage level shifter Rashmi Sharma, Shyam Akashe Proceedings of the International Conference on Innovative Applications of Computational Intelligence on Power Energy and Controls with their Impact on Humanity Cipech 2014, 2014
Hybrid CMOS-memristor 4T-NVSRAM cell for low power applications Atibhi Jadon, Shyam Akashe Proceedings of the International Conference on Innovative Applications of Computational Intelligence on Power Energy and Controls with their Impact on Humanity Cipech 2014, 2014
Optimized power performance and simulation of reversible logic multiplexer Satish Sharma, Shyam Babu Singh, Shyam Akashe 2013 Annual International Conference on Emerging Research Areas Aicera 2013 and 2013 International Conference on Microelectronics Communications and Renewable Energy Icmicr 2013 Proceedings, 2013
Nano-scale silicon MOSFETs: Modelling and simulation challenges in the ballistic limit Aditya Dayal, Anuj Kr. Shrivastava, Abhay Vidyarthi, Shyam Akashe 2013 Annual International Conference on Emerging Research Areas Aicera 2013 and 2013 International Conference on Microelectronics Communications and Renewable Energy Icmicr 2013 Proceedings, 2013
Multiple-gate silicon on insulator (SOI) MOSFETs: Device design and analysis Aditya Dayal, Satya Prakash Pandey, Saurabh Khandelwal, Shyam Akashe 2013 Annual International Conference on Emerging Research Areas Aicera 2013 and 2013 International Conference on Microelectronics Communications and Renewable Energy Icmicr 2013 Proceedings, 2013
Leakage reduction in 7T using SVL scheme Gaurav Dixit, Shyam Akashe Proceedings 2012 2nd International Conference on Advanced Computing and Communication Technologies Acct 2012, 2012
Impact of design parameter on SRAM bit cell Jayram Shrivas, Shyam Akashe Proceedings 2012 2nd International Conference on Advanced Computing and Communication Technologies Acct 2012, 2012
