Sriram S R
@srmeaswari.ac.in
Assistant Professor and ECE
SRM Easwari Engineering College
RESEARCH INTERESTS
Nanoelectronics - Modeling and simulaiton of nanoscale Multi-gate MOSFET, FinFET, TFET HEMT etc
Scopus Publications
Scopus Publications
S. R. Sriram and B. Bindu
Springer Science and Business Media LLC
The line-edge roughness (LER) has become one of the dominant sources of process variations in multi-gate transistors. The estimation of threshold voltage distribution due to LER through atomistic simulations is computationally intensive, even though these simulations provide accurate results. In this paper, a physics-based model for channel LER-induced threshold voltage fluctuations due to variations of the silicon-body thickness in a double-gate (DG) MOSFET is presented. The developed $$V_\\mathrm{TH}$$ V TH model gives more insights into the dependence of device and LER parameters on the $$V_\\mathrm{TH}$$ V TH variations with a reduced computational time. The computed $$V_\\mathrm{TH}$$ V TH variations due to different LER patterns are validated with TCAD simulations. The threshold voltage standard deviation due to LER in 500 device samples for different device dimensions, doping concentration and biases is studied. The developed model can be easily integrated in any circuit simulator to predict the threshold voltage variations of the devices due to LER.
Y. M. Aneesh, S. R. Sriram, K. R. Pasupathy, and B. Bindu
Institute of Electrical and Electronics Engineers (IEEE)
In this paper, a physics-based bias-dependent model of single-event transients (SETs) in double-gate (DG) MOSFET suitable for circuit simulation is presented. The existing approaches that use double exponential and dual double-exponential current sources to emulate these transient currents in the circuit simulators depend on the parameters extracted from TCAD device simulations. In order to capture the essential physics behind these current transients in the circuit simulations, there is a need for a physics-based bias-dependent SET current model that considers the electrostatics in the chosen device. The proposed SET current model is developed from the solution of 2-D Poisson’s equation with proper boundary conditions of DG MOSFET. It takes into account the dependence of the transient potential and drain current on linear energy transfer (LET), strike positions, drain and gate biases, device dimensions, and channel doping. The results from the model are validated with the simulation results from TCAD. The SET current model is integrated in Cadence circuit simulator and observed through simulations the voltage perturbation at the output of the CMOS inverter due to heavy ion strike on nMOS transistor in OFF state for different LETs and loads. The proposed model captures the current plateau region effect in CMOS inverter.
Sriram S.R. and Bindu B.
Elsevier BV
Abstract An analytical model of threshold voltage fluctuations due to random discrete traps at Si/SiO2 interface and in gate oxide regions for undoped double-gate (DG) MOSFET with high-k/SiO2 gate dielectric stack is presented in this paper. The model is derived based on the solution of 2-D Poisson's equation considering both position and number fluctuation of traps. The distribution of traps at the Si/SiO2 interfaces and in both gate oxide regions in double-gate structure are obtained using the bivariate Poisson distribution. The impact of interface and oxide traps over the threshold voltage are analyzed separately and together for the samples of 500 devices. The results from the model are verified using 2-D TCAD simulation results for different trap position, trap density, device dimension and drain bias. Even though the variability due to traps present in the gate oxide is comparatively lesser than the interface traps, the effect of oxide traps located in the interfacial layer (SiO2) cannot be neglected. The device variability increases with the consideration of both interface and oxide traps simultaneously and the threshold voltage fluctuations (ΔVTH) reach maximum of 90 mV. The proposed model takes less computational time for the calculation of threshold voltage fluctuations due to discrete traps compared to the atomistic simulations and thus it is suitable for circuit simulation.
S. R. Sriram and B. Bindu
Institute of Electrical and Electronics Engineers (IEEE)
In this paper, a physics-based threshold voltage model of symmetrical double gate (DG) MOSFET, including the random dopants in the channel is presented. The model is derived from the solution of 2-D Poisson’s equation and is suitable for circuit simulation. The average potential considering random dopants in the channel is used to calculate the threshold voltage and provides accurate results. The developed threshold voltage model is validated with TCAD simulations for different device dimensions and doping concentrations. The standard deviation (<inline-formula> <tex-math notation="LaTeX">${\\sigma } {\\text{V}}_{\\text{TH}}$ </tex-math></inline-formula>) is calculated from a threshold voltage distribution of 200 devices. The proposed model is useful to simulate variations in a large number of devices with randomly placed dopants, with less computational time. The model is integrated in the Cadence circuit simulator and analyzed the effect of random dopant fluctuation-induced <inline-formula> <tex-math notation="LaTeX">${\\text{V}}_{\\text{TH}}$ </tex-math></inline-formula> variations of n-channel DG MOSFET in the inverter circuit.
S. R. Sriram and B. Bindu
Springer Science and Business Media LLC
A threshold voltage model based on the solution of the three-dimensional (3-D) Poisson’s equation for an undoped triple-gate (TG) fin-shaped field-effect transistor (FinFET) with localized interface trapped charge is presented in this paper. Such localized interface charge created by either hot carrier injection or bias temperature instability degrades the threshold voltage and thereby the overall performance of FinFET devices. The proposed model considers the location of the interface traps and the length of the damaged region. The potential distribution and the threshold voltage of the TG FinFET obtained from the model are compared with data from technology computer-aided design simulations, which validates the model for different device dimensions, interface trapped charge densities, damaged region lengths, and drain biases. The results show that the variation of the threshold voltage mainly depends on the length of the damaged region and the thickness of the oxide but is independent of the fin width and height. Furthermore, short-channel effects such as threshold voltage roll-off and drain-induced barrier lowering are investigated, considering both positive and negative interface traps.
S. R. Sriram and B. Bindu
IEEE
Hot Carrier Injection is one of the serious reliability issues of the NMOS transistors in the nanoscale regime. The effect of channel strain on hot carrier reliability of 45 nm strained Si/relaxed Si1−xGex CMOS and its impact in inverter and SRAM cell is presented in this paper. The introduction of the strain in the MOSFET boosts the impact ionization and hot carrier injection in the NMOS transistors. The existing hot carrier (HC) model of n-channel MOSFET is modified by incorporating mole fraction dependent impact ionization rate of strained Si MOSFET and the results are validated using TCAD simulations. The degradation of the inverter and SRAM cell due to HCI is analyzed using Cadence circuit simulator including the estimated threshold voltage variations in affected NMOS transistors. The 6T-SRAM cell and the inverter is designed using the strained CMOS technology. The effect of HC degradation in strained n-channel MOSFET on the static, read and write noise margins of the SRAM cell is analyzed. The noise margins which are improved by stronger pull down network designed with strained n-channel MOSFETs found to be degraded after the hot carrier stress. It is also observed that in strained CMOS inverter, the propagation delay is degraded due to HC injection in the higher rate than in the unstrained CMOS inverter.
S. R. Sriram and B. Bindu
IEEE
The statistical variability in nano-scaled devices due to line-edge roughness (LER) is a major challenge for further scaling of device dimensions in multi-gate FETs. The LER in Double-Gate (DG) MOSFET is mainly due to silicon body thickness fluctuations (BTF) and oxide thickness fluctuations (OTF) along the channel direction. The effect of variation of channel length along the width direction (gate LER) is negligible in this device. In this paper, the threshold voltage (VTH) fluctuations due to BTF and OTF in 30-nm DG MOSFET are analyzed for various device parameters and supply voltage through TCAD simulations. The devices with intrinsic channel and shorter gate length are found to have larger threshold voltage fluctuations due to LER.
S. R. Sriram and B. Bindu
Springer Science and Business Media LLC
The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this should be taken care for reliable circuit design. The introduction of uniaxial strain in the channel of FinFET to enhance the performance further limits the reliable design of VLSI circuits. Hence, there is a great need to capture these device-level variations in circuits through physics-based models. In this paper, one such analytical model of hot carrier (HC) degradation in uniaxial strained TG FinFET based on reaction–diffusion mechanism is developed, considering various geometrical aspects of the device, for the first time. The developed model is validated using experimentally calibrated Sentaurus TCAD simulation results. The results show that the strain in the channel worsens the degradation of threshold voltage due to HCI. The developed model is integrated in Cadence circuit simulator, and the impact of HC degradation in strained TG FinFET-based CMOS NAND logic circuit is analyzed.
S. R. Sriram and B. Bindu
IEEE
The Negative Bias Temperature Instability (NBTI) is one of the serious reliability issues of the p-type MOS based transistors. The downscaling of gate oxide thickness to reestablish the gate voltage controllability over the channel adversely affects the reliability of the devices and circuits. The multigate transistors such as FinFET which shows superior device scalability over the planar MOSFET are also severely affected by the NBTI effects in the nanoscale regime. The time to digital converter (TDC) is a signal conditioning circuit which is used to convert the specified time interval between two events into the digital codes. The proper functioning of the TDC is based on accuracy of the propagation delay of its designed delay lines. The degradation of the delay in the delay lines due to NBTI lead to improper code conversions. The Vernier delay line TDC is designed using the 30 nm Triple Gate FinFET technology with high resolution of 10 ps. The effect of NBTI degradation over the FinFET based Vernier delay line TDC in the critical nodes is analyzed. The occurrence of offset error, increase in the non linearity and degradation of resolution are observed due to the NBTI degradation.
Sriram S.R. and Bindu B.
Elsevier BV
Sobhana Tayenjam, S. R. Sriram, and B. Bindu
IEEE
Miniaturization in the geometry of CMOS technology improves IC performance but beyond certain limit, scaling of CMOS may be quite challenging due to various short channel effects. To overcome such issues double gate (DG) CMOS or FinFET are used because of its ability to minimize short channel effects. This paper presents the designing of frequency synthesizer using phase locked loop (PLL) based on FinFET technology. Here we have used shorted gate FinFET for designing the circuits. A frequency synthesizer capable of synthesizing an input clock frequency of 500 MHz to an output frequency of 1 GHz is implemented using FinFET with a lock in time of 254 ns. The circuits are implemented on Cadence ®Virtuoso using 32nm FinFET technology and 1V power supply.