Sarosij Adak

@bbit.edu.in

Electronics & Communication Engineering
Budge Budge Institute Of Technology

Sarosij Adak


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https://researchid.co/sarosijadak
27

Scopus Publications

403

Scholar Citations

12

Scholar h-index

15

Scholar i10-index

Scopus Publications

  • Performance Analysis of Gate Stack DG-MOSFET for Biosensor Applications
    Saradiya Kishor Parija, Sanjit Kumar Swain, Sudhansu Mohan Biswal, Sarosij Adak, Pradipta Dutta
    Silicon, 2022
    In this paper the performance of gate stack metal oxide semiconductor field effect transistor (MOSFET) is investigated with respect to different bio molecules for application as biosensor device. In order to beat the limits of short channel effects (SCEs) the double gate stack MOSFET has been preferred as the proposed device. For biosensor application, dielectric modulation technique has been chosen and effect of different bio molecules like protein, biotin, streptavidin, APTES, etc. are studied to verify the sensitivity as a biosensor for this proposed device. The sensitivity parameter and analog/Rf parameter have been studied for different bio-molecules and a comparative result has been established. The sensitivity of bimolecules located in the cavity side by the oxide region is observed in the variation of threshold voltage and also different analog and RF parameters which can be used for future application in the area of medical science. Two oxide layer one is high k(HfO 2 ) and low k(SiO 2 ) has been used for stacking. For simulations, 2D Sentrausu TCAD simulator has been used.
  • Comparison Study of DG-MOSFET with and without Gate Stack Configuration for Biosensor Applications
    Saradiya Kishor Parija, Sanjit Kumar Swain, Sarosij Adak, Sudhansu Mohan Biswal, Pradipta Dutta
    Silicon, 2022
    In this Paper, we have studied and compared the performance of two different configurations of simulation model advanced MOSFET devices which can be used for biosensor application. The bio-molecules like protein, biotin, streptavidin, APTES, etc., undergo label free electrical detection with the help of dielectrical modulation technique in order to overcome the limitations of short channel effect in a more efficient way. The bio-molecules trapped inside the cavity region change the electrical parameters of the MOSFET. Biosensors based on MOSFETs have certain issues, like short channel effects (SCEs) and problems related to scaling and power supply. Therefore the proposed device is better withstand to SCEs and can be consider as an alternative for biosensing applications. For channel material, silicon is used for both the configurations i.e. with stack and without stack model and we have also studied the performance of the device based on the analog as well as RF parameters by considering the protein as bio-molecule in the cavity. Two different oxide materials are used to design the device structure such as HfO2 (K = 25) and SiO2 (K = 3.9) and for simulation purpose the 2D Sentrausu TCAD simulator has been used. The sensing capability of this proposed dielectric modulated device can be applicable for IOT based applications. They can also be uses in health IOT systems for medical research applications and as bio chip sensor in wearable device so as to study the protein content of the human body.
  • Performance enhancement of normally off InAlN/AlN/GaN HEMT using aluminium gallium nitride back barrier
    Nisarga Chand, Sarosij Adak, S.K. Swain, Sudhansu Mohan Biswal, A. Sarkar
    Computers and Electrical Engineering, 2022
  • Comparative study on Analog RF Parameter of InAlN/AlN/GaN Normally off HEMTs with and without AlGaN back barrier
    Nisarga Chand, Sanjit Kumar Swain, Sudhansu Mohan Biswal, Angsuman Sarkar, Sarosij Adak
    Proceedings of 4th International Conference on 2021 Devices for Integrated Circuit Devic 2021, 2021
    In this work, we have made a relative assessment of lattice-matched In0.17Al0.83N/AlN/GaN normally off HEMT device with AlGaN back-barrier (BB) and without back-barrier by using device simulator. The utility of AlGaN BB on the said E-HEMT relaxes the channel, which reduces the short channel effects. It also reduces the total gate capacitance and simultaneously improves the cut- off frequency. The numerical modelings are done by the 2Dimenssional TCAD by means of HD mobility and matched with the previously accepted experimental result. Different device parameters are analyzed and compared with BB and without BB with the help of the numerical modeling. AlGaN back-barrier has further benefits in device parameters with comparison to without back-barrier i.e. less total gate capacitance and higher cut-off frequency. These outcomes prove the utility of proposed BB in such E-Mode GaN HEMTs can be a substitute way out in support of high power along with high-frequency purposes.
  • Study of Linearity Performance of Graded Channel Gate Stacks Double Gate MOSFET with Respect to High-K Oxide Thickness
    Sanjit Kumar Swain, Satish Kumar Das, Sarosij Adak
    Silicon, 2020
    In this paper a double gate MOSFET having non uniform channel doping with gate stack structure is explored to study the linearity analysis. The extractions of linearity parameters confirm the novelty of the device and also enable us to achieve better the analog/RF applications. This promising device has an advantage of showing higher cut-off frequency, reduced DIBL, better gate oxide reliability and limiting the effects of parasitic bipolar phenomenon. In this paper we have studied the detail analysis of important linearity parameters of this proposed device with respect to change in high K oxide thickness (t oxh ) to have clear ideas on different linearity parameters like VIP2, VIP3, IIP3 and IMD3 and their variations. The simulated results validate that the change in t oxh of this device plays a significant role on improving the linearity performance and there by careful optimization of this parameters can infer achieving better and reliable analog/linearity performances for SOC applications.
  • Performance comparison of inas based dg-mosfet with respect to sio2 and gate stack configuration
    Sanjit K. Swain, Sudhansu M. Biswal, Satish K. Das, Sarosij Adak, Biswajit Baral
    Nanoscience and Nanotechnology Asia, 2020
    Objective:: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have been analyzed by considering InAs as a channel material. Methods: For the very first time, gate stack techniques in this device have been incorporated and a comparative analysis is conducted with respect to SiO2 oxide layer. The variations in different patterns of oxide layer and their comparison have been thoroughly investigated to have a better understanding of various performance parameters. A thorough analysis of the key figure-of-merits such as trans-conductance factor, transconductance generation factor (TGF), gate capacitance, cutoff frequency (fT), maximum frequency of oscillation (fmax), GBW and various linearity parameters such as gm2, gm3,VIP2, VIP3, IIP3, has been studied with respect to SiO2 oxide material and gate stack technology. Result:: The simulation results revealed that the performances of the device are sensitive to both the oxide materials and it was also inferred that gate stack technology gave a better performance over SiO2 oxide layer. Conclusion:: These results have significant effects in analog, RF and linearity operations. In this work, computer aided design (TCAD) simulations by 2D ATLAS, Silvaco International have been used.
  • Impact of high-K dielectric materials on performance analysis of underlap in 0. 1 7 Al 0. 8 3 N/GaN DG-MOSHEMTs
    Sarosij Adak, Sanjit Kumar Swain
    Nano, 2019
    This work systematically investigated the effect of high-[Formula: see text] oxide materials on the performance of InAlN/GaN heterostructure underlap double gate (DG) MOS-HEMTs by considering 2D Sentaurus TCAD simulation. During the course of simulation, hydrodynamic mobility model was implemented and the obtained results were used for validating the model with the previously published experimental results. Different device performance parameters are thoroughly studied for different high-[Formula: see text] oxide materials by performing extensive simulations. It is verified that short channel effects (SCEs), key analog and RF figures of merits parameters and [Formula: see text]th improved with an increase in the value of high-[Formula: see text] oxide material. Moreover, it is also revealed that there is a significant growth in the values of key analog and RF figures of merits with respect to high-[Formula: see text] values. This analysis suggested that use of a suitable value of high-[Formula: see text]-valued oxide material in InAlN/GaN heterostructure underlap DG MOS-HEMTs can be one of the alternatives for future high speed and microwave applications.
  • Effect of AlGaN Back Barrier on InAlN/AlN/GaN E-Mode HEMTs
    Sarosij Adak, Nisarga Chand, Sanjit Kumar Swain, Angsuman Sarkar
    Proceedings of 3rd International Conference on 2019 Devices for Integrated Circuit Devic 2019, 2019
    This paper reports the effect of AlGaN back barrier on the performance of lattice matched In0.17Al0.83N/AlN/GaN Recess Gate E HEMT Device. The use of AlGaN back barrier on this device relaxes the GaN channel, which in turn limits the SCEs. Moreover reduced the leakage current through gate (Ig) and simultaneously improves carrier confinement and off state breakdown voltage. The numerical modeling are carried out with the help of 2D Sentaurus TCAD simulator using Hydrodynamic model, which is standardized with respect to already published fabricated results. Different performance parameters are studied using the simulations and a wide comparison was done with and without considering AlGaN back barrier (BB). Addition of AlGaN BB has added benefits in performance parameters w.r.t without BB i.e. threshold voltage raised to 0.93 volt with respect to 0.75 volt, drop in DIBL from 100mv/V to 36mv/V and substantial reduction in gate leakage current. These results reveal that use of AlGaN BB in such devices can be an alternative solution for high power and high frequency switching applications.
  • Effect of High-K Spacer on the Performance of Non-Uniformly doped DG-MOSFET
    Sanjit K Swain, Satish K Das, Sudhansu M Biswal, Sarosij Adak, Umakanta Nanda, Asmit Amlan Sahoo, Debasish Navak, Biswajit Baral, Dhananjaya Tripathy
    Proceedings of 3rd International Conference on 2019 Devices for Integrated Circuit Devic 2019, 2019
    This paper presents the performance of non-uniformed doped double gate (DG) MOSFET with different spacer variations with an aim to analysis the effects of short channel and various performance metrics. In this work we have taken silicon as the channel material with non-uniform doping for studying the analog and RF performances. Spacer's materials having different permittivities were used to understand their effect on the device performance. Based on the simulations, we can conclude that analog and Radio Frequency performance of the device shows an significant improvement with addition of spacer layer. We have used computer aided design (TCAD) simulations by SILVACO International.
  • Comparison of Linearity Performance of InAs Based DG-MOSFETs with Gate Stack, SiO2 and HfO2
    Sanjit Kumar Swain, Sarosij Adak, Sudhansu Mohan Biswal, Biswajit Baral, Saradiya Parija
    Proceedings of International Conference on 2018 IEEE Electron Device Kolkata Conference Edkcon 2018, 2018
    This work demonstrates a comparative analysis of various types of Double-Gate MOSFET, aims at enhancing the analog, linearity performances and these devices are more protective to short-channel effects (SECs). We have studied the linearity performance of DG-MOSFET by considering channel material as InAs and simultaneously incorporating gate stack technique. Variations oxide materials by considering channel as InAs and finally their comparison were thoroughly studied to have a better understanding of different linearity parameters. Various Figure-of-merits(FOMs) such as trans-conductance factor, VIP2, VIP3, IIP3 are thoroughly analysed for various high-K oxide materials along with gate stack technology. From the simulation results it is found that the performances of the device changes with respect to change in different oxide materials and it is also inferred that gate stack technology has also significant effect in the linearity performances. In this work, we have used the (TCAD) simulations by 2D ATLAS, Silvaco International to carry out the simulations.
  • Study of Linearity Performances of Junction-less Triple-Material Cylindrical Surrounding Gate MOSFET
    Pradipta Kumar Jena, Sanjit Kumar Swain, Omprakash Acharya, Sarosij Adak
    2018 International Conference on Applied Electromagnetics Signal Processing and Communication Aespc 2018, 2018
  • Sub threshold analog &RF parameter extraction of graded channel gate stack DG-MOSFETs with high K material using NQS approach
    Sanjit Kumar Swain, Sarosij Adak, Saradiya Parija, Chandan Kumar Sarkar
    Proceedings of 2nd International Conference on 2017 Devices for Integrated Circuit Devic 2017, 2017
  • Effect of doping in p-GaN gate on DC performances of AlGaN/GaN normally-off scaled HFETs
    Sarosij Adak, Sanjit Kumar Swain, Hafizur Rahaman, Chandan Kumar Sarkar
    Proceedings of 2nd International Conference on 2017 Devices for Integrated Circuit Devic 2017, 2017
  • Nanotechnology applications in electron devices
    S. Roy, C. K. Ghosh, C. Sarkar
    Nanotechnology Synthesis to Applications, 2017
  • Effect of barrier thickness on linearity of underlap AlInN/GaN DG-MOSHEMTs
    Sarosij Adak, Sanjit Kumar Swain, Hemant Pardeshi, Hafizur Rahaman, Chandan Kumar Sarkar
    Nano, 2017
  • Impact of gate engineering in enhancement mode n++GaN/InAlN/AlN/GaN HEMTs
    Sarosij Adak, Sanjit Kumar Swain, Hafizur Rahaman, Chandan Kumar Sarkar
    Superlattices and Microstructures, 2016
  • Performance analysis of gate material engineering in enhancement mode n++GaN/InAlN/AlN/GaN HEMTs
    Sarosij Adak, Sanjit Kumar Swain, Godwin Raj, Hafizur Rahaman, Chandan Kumar Sarkar
    Proceedings of the 3rd International Conference on Devices Circuits and Systems Icdcs 2016, 2016
  • Impact of high K layer material on Analog/RF performance of forward and reversed Graded channel Gate Stack DG-MOSFETs
    Sanjit Kumar Swain, Sarosij Adak, Arka Dutta, Godwin Raj, Chandan Kumar Sarkar
    Proceedings of the 3rd International Conference on Devices Circuits and Systems Icdcs 2016, 2016
  • Impact of InGaN back barrier layer on performance of AIInN/AlN/GaN MOS-HEMTs
    Sanjit Kumar Swain, Sarosij Adak, Sudhansu Kumar Pati, Chandan Kumar Sarkar
    Superlattices and Microstructures, 2016
  • Influence of channel length and High-K oxide thickness on Subthreshold DC performance of graded channel and gate stack DG-MOSFETs
    Sarosij Adak, Sanjit Kumar Swain, Arka Dutta, Hafizur Rahaman, Chandan Kumar Sarkar
    Nano, 2016
  • Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs
    Sanjit Kumar Swain, Arka Dutta, Sarosij Adak, Sudhansu Kumar Pati, Chandan Kumar Sarkar
    Microelectronics Reliability, 2016
  • Effect of channel thickness and doping concentration on sub-threshold performance of Graded channel and Gate stack DG MOSFETs
    Sanjit Kumar Swain, Sarosij Adak, Bikash Sharma, Sudhansu Kumar Pati, Chandan Kumar Sarkar
    Journal of Low Power Electronics, 2015
  • Effect of AlN spacer layer thickness on device performance of AIInN/AlN/GaN MOSHEMT
    Sarosij Adak, Sanjit Kumar Swain, Hemant Pardeshi, Hafizur Rahman, Chandan Kumar Sarkar
    Proceedings 1st International Conference on Computing Communication Control and Automation Iccubea 2015, 2015
  • Comparative assesment of ground plane and strained based FDSOI MOSFET
    Informacije MIDEM, 2015
  • Analysis of flicker and thermal noise in p-channel Underlap DG FinFET
    Sanjit Kumar Swain, Sarosij Adak, Sudhansu Kumar Pati, Hemant Pardeshi, Chandan Kumar Sarkar
    Microelectronics Reliability, 2014
  • High performance AlInN/AlN/GaN p-GaN back barrier Gate-Recessed Enhancement-Mode HEMT
    Sarosij Adak, Arghyadeep Sarkar, Sanjit Swain, Hemant Pardeshi, Sudhansu Kumar Pati, Chandan Kumar Sarkar
    Superlattices and Microstructures, 2014
  • Study of HfAlO/AlGaN/GaN MOS-HEMT with source field plate structure for improved breakdown voltage
    Sarosij Adak, Sanjit Kumar Swain, Avtar Singh, Hemant Pardeshi, Sudhansu Kumar Pati, Chandan Kumar Sarkar
    Physica E Low Dimensional Systems and Nanostructures, 2014

RECENT SCHOLAR PUBLICATIONS

  • Performance analysis of gate stack DG-MOSFET for biosensor applications
    SK Parija, SK Swain, SM Biswal, S Adak, P Dutta
    Silicon 14 (14), 8371-8379 , 2022
    2022
    Citations: 18
  • Comparison study of DG-MOSFET with and without gate stack configuration for biosensor applications
    SK Parija, SK Swain, S Adak, SM Biswal, P Dutta
    Silicon 14 (7), 3629-3640 , 2022
    2022
    Citations: 13
  • Performance enhancement of normally off InAlN/AlN/GaN HEMT using aluminium gallium nitride back barrier
    N Chand, S Adak, SK Swain, SM Biswal, A Sarkar
    Computers & Electrical Engineering 98, 107695 , 2022
    2022
    Citations: 11
  • Comparative study on analog & RF parameter of InALN/AlN/GaN normally off HEMTs with and without AlGAN back barrier
    N Chand, SK Swain, SM Biswal, A Sarkar, S Adak
    2021 Devices for Integrated Circuit (DevIC), 616-620 , 2021
    2021
    Citations: 8
  • Performance Comparison of InAs Based DG-MOSFET with Respect to SiO2 and Gate Stack Configuration
    SK Swain, SM Biswal, SK Das, S Adak, B Baral
    Nanoscience & Nanotechnology-Asia 10 (4), 419-424 , 2020
    2020
    Citations: 1
  • Study of linearity performance of graded channel gate stacks double gate MOSFET with respect to high-K oxide thickness
    SK Swain, SK Das, S Adak
    Silicon 12 (7), 1567-1574 , 2020
    2020
    Citations: 17
  • Effect of High-K Spacer on the Performance of Non-Uniformly doped DG-MOSFET
    SK Swain, SK Das, SM Biswal, S Adak, AAS Umakanta Nanda, D Navak, ...
    Devices for Integrated Circuit (DevIC) , 2019
    2019
    Citations: 14
  • Effect of AlGaN Back Barrier on InAlN/AlN/GaN E-Mode HEMTs
    S Adak, N Chand, SK Swain, A Sarkar
    Devices for Integrated Circuit (DevIC) , 2019
    2019
    Citations: 10
  • Impact of high-K dielectric materials on performance analysis of underlap In0.17Al0.83N/GaN DG-MOSHEMTs
    S Adak
    Nano , 2019
    2019
    Citations: 5
  • Comparison of Linearity Performance of InAs Based DG-MOSFETs with Gate Stack, SiO2 and HfO2
    SP Sanjit Kumar Swain, Sarosij Adak, Sudhansu Mohan Biswal, Biswajit Baral
    2018 IEEE Electron Device Kolkata Conference (EDKCON) , 2018
    2018
    Citations: 4
  • Study of Linearity Performances of Junction-less Triple-Material Cylindrical Surrounding Gate MOSFET
    PK Jena, SK Swain, O Acharya, S Adak
    2018 International Conference on Applied Electromagnetics, Signal Processing … , 2018
    2018
    Citations: 2
  • Analysis of GaN based Heterostructure Nano Devices
    S Adak
    IIEST Shibpur, , 2018
    2018
  • Performance study of GCGS DG-MOSFETs for asymmetric doping and high K oxide material using NQS method
    SK Swain, S Adak, S Parija, CK Sarkar
    Journal of Active and Passive Electronic Devices 13 (2-3), 149-163 , 2018
    2018
    Citations: 2
  • Nanotechnology Applications in Electron Devices
    CKS Sarosij Adak, Arghyadeep Sarkar, Sanjit Kumar Swain, Sunipa Roy, Chandan ...
    Nanotechnology , 2017
    2017
    Citations: 1
  • Nanotechnology: synthesis to applications
    S Roy, CK Ghosh, CK Sarkar
    CRC Press , 2017
    2017
    Citations: 48
  • Performance study of GCGS DG-MOSFETs for Asymmetric Doping and High K Oxide Material Using NQS Method
    CKS Sanjit Kumar Swain, Sarosij Adak, Saradiya Parija
    J. of Active and Passive Electronic Devices , 2017
    2017
  • Effect of doping in p-GaN gate on DC performances of AlGaN/GaN normally-off scaled HFETs
    S Adak, SK Swain, H Rahaman, CK Sarkar
    2017 Devices for Integrated Circuit (DevIC), 372-375 , 2017
    2017
    Citations: 6
  • Sub threshold analog &RF parameter extraction of graded channel gate stack DG-MOSFETs with high K material using NQS approach
    SK Swain, S Adak, S Parija, CK Sarkar
    2017 Devices for Integrated Circuit (DevIC), 216-220 , 2017
    2017
  • Effect of barrier thickness on linearity of underlap AlInN/GaN DG-MOSHEMTs
    S Adak, SK Swain, H Pardeshi, H Rahaman, CK Sarkar
    Nano 12 (01), 1750009 , 2017
    2017
    Citations: 2
  • Impact of gate engineering in enhancement mode n++ GaN/InAlN/AlN/GaN HEMTs
    S Adak, SK Swain, H Rahaman, CK Sarkar
    Superlattices and Microstructures 100, 306-314 , 2016
    2016
    Citations: 16

MOST CITED SCHOLAR PUBLICATIONS

  • High performance AlInN/AlN/GaN p-GaN back barrier gate-recessed enhancement-mode HEMT
    S Adak, A Sarkar, S Swain, H Pardeshi, SK Pati, CK Sarkar
    Superlattices and Microstructures 75, 347-357 , 2014
    2014
    Citations: 51
  • Nanotechnology: synthesis to applications
    S Roy, CK Ghosh, CK Sarkar
    CRC Press , 2017
    2017
    Citations: 48
  • Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs
    SK Swain, A Dutta, S Adak, SK Pati, CK Sarkar
    Microelectronics Reliability 61, 24-29 , 2016
    2016
    Citations: 47
  • Impact of InGaN back barrier layer on performance of AIInN/AlN/GaN MOS-HEMTs
    SK Swain, S Adak, SK Pati, CK Sarkar
    Superlattices and Microstructures 97, 258-267 , 2016
    2016
    Citations: 33
  • Study of HfAlO/AlGaN/GaN MOS-HEMT with source field plate structure for improved breakdown voltage
    S Adak, SK Swain, A Singh, H Pardeshi, SK Pati, CK Sarkar
    Physica E: Low-dimensional Systems and Nanostructures 64, 152-157 , 2014
    2014
    Citations: 25
  • Performance analysis of gate stack DG-MOSFET for biosensor applications
    SK Parija, SK Swain, SM Biswal, S Adak, P Dutta
    Silicon 14 (14), 8371-8379 , 2022
    2022
    Citations: 18
  • Effect of channel thickness and doping concentration on sub-threshold performance of Graded Channel and gate stack DG MOSFETs
    SK Swain, S Adak, B Sharma, SK Pati, CK Sarkar
    Journal of Low Power Electronics 11 (3), 366-372 , 2015
    2015
    Citations: 18
  • Study of linearity performance of graded channel gate stacks double gate MOSFET with respect to high-K oxide thickness
    SK Swain, SK Das, S Adak
    Silicon 12 (7), 1567-1574 , 2020
    2020
    Citations: 17
  • Impact of gate engineering in enhancement mode n++ GaN/InAlN/AlN/GaN HEMTs
    S Adak, SK Swain, H Rahaman, CK Sarkar
    Superlattices and Microstructures 100, 306-314 , 2016
    2016
    Citations: 16
  • Influence of channel length and high-K oxide thickness on subthreshold DC performance of graded channel and gate stack DG-MOSFETs
    S Adak, SK Swain, A Dutta, H Rahaman, CK Sarkar
    Nano 11 (09), 1650101 , 2016
    2016
    Citations: 16
  • Effect of High-K Spacer on the Performance of Non-Uniformly doped DG-MOSFET
    SK Swain, SK Das, SM Biswal, S Adak, AAS Umakanta Nanda, D Navak, ...
    Devices for Integrated Circuit (DevIC) , 2019
    2019
    Citations: 14
  • Comparison study of DG-MOSFET with and without gate stack configuration for biosensor applications
    SK Parija, SK Swain, S Adak, SM Biswal, P Dutta
    Silicon 14 (7), 3629-3640 , 2022
    2022
    Citations: 13
  • Comparative assesment of ground plane and strained based FDSOI MOSFET
    A Singh, S Adak, H Pardeshi, A Sarkar, CK Sarkar
    Informacije MIDEM 45 (1), 73-79 , 2015
    2015
    Citations: 12
  • Performance enhancement of normally off InAlN/AlN/GaN HEMT using aluminium gallium nitride back barrier
    N Chand, S Adak, SK Swain, SM Biswal, A Sarkar
    Computers & Electrical Engineering 98, 107695 , 2022
    2022
    Citations: 11
  • Effect of AlGaN Back Barrier on InAlN/AlN/GaN E-Mode HEMTs
    S Adak, N Chand, SK Swain, A Sarkar
    Devices for Integrated Circuit (DevIC) , 2019
    2019
    Citations: 10
  • Comparative study on analog & RF parameter of InALN/AlN/GaN normally off HEMTs with and without AlGAN back barrier
    N Chand, SK Swain, SM Biswal, A Sarkar, S Adak
    2021 Devices for Integrated Circuit (DevIC), 616-620 , 2021
    2021
    Citations: 8
  • Effect of AlN spacer layer thickness on device performance of AIInN/AlN/GaN MOSHEMT
    S Adak, SK Swain, H Pardeshi, H Rahman, CK Sarkar
    2015 International Conference on Computing Communication Control and … , 2015
    2015
    Citations: 7
  • Effect of doping in p-GaN gate on DC performances of AlGaN/GaN normally-off scaled HFETs
    S Adak, SK Swain, H Rahaman, CK Sarkar
    2017 Devices for Integrated Circuit (DevIC), 372-375 , 2017
    2017
    Citations: 6
  • OFDMA-PON: High Speed PON Access System
    S Biswas, S Adak
    International Journal of Soft Computing 1 , 2010
    2010
    Citations: 6
  • Impact of high-K dielectric materials on performance analysis of underlap In0.17Al0.83N/GaN DG-MOSHEMTs
    S Adak
    Nano , 2019
    2019
    Citations: 5