Vijayakumar Devarakonda

@iiitk.ac.in

Assistant Professor, Department of Electronics and Communication Engineering
Indian Institute of Information Technology Design and Manufacturing Kurnool (IIITDM, Kurnool)

Vijayakumar Devarakonda


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https://researchid.co/vdevarakonda.ece

EDUCATION

Doctor of Philosophy - Electronics Engineering from Indian Institute of Technology (Banaras Hindu University), Varanasi
Master of Technology - Electronics Engineering with Specialization in Microelectronics from Indian Institute of Technology (Banaras Hindu University), Varanasi
Bachelor of Technology - Electronics and Communication Engineering from Malaviya National Institute of Technology, Jaipur

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering
6

Scopus Publications

21

Scholar Citations

2

Scholar h-index

1

Scholar i10-index

Scopus Publications

  • Implementation of Digital Logic Gate Families Using Low Operating Flexible Organic TFT Based on Innovative Compact Modeling Approach
    Mukuljeet Singh Mehrolia, Ashwini Kumar Mishra, Rasveen Singh, Surendra Yadav, Vijayakumar Devarakonda, Abhishek Kumar Singh
    3rd IEEE International Conference on Industrial Electronics Developments and Applications Icidea 2025, 2025
    The article demonstrates the brief fabrication method of the flexible organic thin film transistor (OTFT) developed earlier and its utilization for the development of various basic logic gates (NAND, NOR, AND, NOT, and OR Gates). The compact modeling of the fabricated device and the implementation of the logic gates has been carried out using Silvaco-Techmodeler and Silvaco-Gateway tools, respectively. The device can operate at -2 V supply with good electrical characteristics in terms of $-2\\mu \\mathrm{A}$ drain current, $\\mathrm{I}_{\\text{ON}}/\\mathrm{I}_{\\text{OFF}}\\sim 10^{3}$ ‘ and $\\mu_{p}\\sim 0.1\\text{cm}^{2}/\\mathrm{V}-\\sec$ respectively. The Silvaco-Gateway tool implements the logic gates with excellent characteristics, demonstrating logic swing of 1.18 V and a delay of 3.7 ns. The logic gates also possess a good transient characteristic with all four possible logic inputs (00, 01, 10, and 11). The Silvaco-Techmodeler tool models the device with an accuracy of approximately 100%, with a 0.07% and 0.08% error between the experimental and modeled data, respectively. The cost-efficiently fabricated solution-processed transistor in this article can be further utilized in the fields of medical and sensing applications.
  • CAM Based With-Memory Computing for ALU Operations
    C Sri Vardhan, B N H Nandan, P Tej Kumar, N Teja Krishna, Rangababu Peesapati, Vijayakumar Devarakonda
    2024 IEEE 21st India Council International Conference Indicon 2024, 2024
    Memory Computing (M-C) is a rapidly growing paradigm designed to overcome the problems caused by traditional Von-Neumann architectures and is highly advantageous for big data computing applications. Leveraging Content Addressable Memory (CAM) to perform memory computing improves the latency and throughput as it can concurrently search through multiple Look-Up Tables (LUTs) containing the precomputed results. SRAM-based CAM design suggests the integration of WMC architectures with rapid search operations, enriching efficiency and performance for various ALU operations. In this work, several arithmetic and logical computations involving word lengths of 32-bit, 64-bit and 128-bit are proposed using Bit-Serial & Word-Parallel (BS-WP) and Bit-Parallel & Word-Serial (BP-WS) techniques. BS-WP can be used for performance efficient operations, while WS-BP can be used for resource efficient operations. Results indicate the maximum operational frequency goes up to 1.85 GHz for the boolean operations. BS-WP approach can obtain a speedup of 2.03 times in terms of frequency for 128-bit addition, achieving an improvement of 50.76% in performance. Also, the power consumption can be reduced upto 86% utilizing BP-WS technique.
  • DLP Based Processing-in-Memory Architecture Leveraging Content Addressable Memory
    C Sri Vardhan, B N H Nandan, P Tej Kumar, N Teja Krishna, Rangababu Peesapati, Vijayakumar Devarakonda
    2024 IEEE 8th International Conference on Information and Communication Technology Cict 2024, 2024
    Processing-in-Memory (PiM) is one of the rapidly growing paradigms in this world of computer architecture, wherein the data is processed and stored simultaneously within the memory. This architecture will enable us to perform big data computing that require complex data transitions between memory and ALU with reduced latency and improved throughput. This scheme utilizes the concept of Data Level Parallelism (DLP), to perform multiple operations with less number of clock cycle using a single instruction. In this paper, ALU operations such as addition, multiplication and logical operations are proposed using PiM with a single instruction by means of fixed memory locations. All the operations are implemented by the concept of Single Instruction Multiple Data (SIMD) techniques. The addition is implemented using the Parallel Adder (PA), while multiplication operations are implemented using the karatsuba multiplier. In this work, parallel addition can be implemented with a frequency of 1.42 GHz within the memory, while parallel multiplications can be implemented at a maximum frequency of 2.31 GHz for $2 \\times 2$ bit multiplication by incorporating the karatsuba technique. These implementations consume maximum resources upto 121268 cells of $\\text{NAND}2 \\times 1$ units when inferred in the form of logic cells. Post-layout implementation resulted in an area of area of $83.25 \\ \\mu m^{2}$ for inferring a 1-bit CAM cell.
  • A proposed graphene-gated semiconductor terahertz detector
    Vijayakumar Devarakonda, Amritanshu Pandey, P. Chakrabarti
    Optik, 2023
  • Enhanced optoelectronic properties of a mercury cadmium telluride based double heterojunction photodetector for terahertz applications
    Vijayakumar Devarakonda, Amritanshu Pandey, Parthasarathi Chakrabarti
    Optik, 2021
  • Performance analysis of N+-CdTe/n0-Hg0.824675Cd0.175325Te/p+-Hg0.824675Cd0.175325Ten-i-p photodetector operating at 30 μm wavelength for terahertz applications
    Vijayakumar Devarakonda, Arun Dev Dhar Dwivedi, Amritanshu Pandey, Parthasarathi Chakrabarti
    Optical and Quantum Electronics, 2020

RECENT SCHOLAR PUBLICATIONS

  • Implementation of Digital Logic Gate Families Using Low Operating Flexible Organic TFT Based on Innovative Compact Modeling Approach
    MS Mehrolia, AK Mishra, R Singh, S Yadav, V Devarakonda, AK Singh
    2025 3rd IEEE International Conference on Industrial Electronics … , 2025
    2025
  • CAM Based With-Memory Computing for ALU Operations
    CS Vardhan, BNH Nandan, PT Kumar, NT Krishna, R Peesapati, ...
    2024 IEEE 21st India Council International Conference (INDICON), 1-6 , 2024
    2024
  • DLP Based Processing-in-Memory Architecture Leveraging Content Addressable Memory
    CS Vardhan, BNH Nandan, PT Kumar, NT Krishna, R Peesapati, ...
    2024 IEEE 8th International Conference on Information and Communication … , 2024
    2024
  • A proposed graphene-gated semiconductor terahertz detector
    V Devarakonda, A Pandey, P Chakrabarti
    Optik 288, 171204 , 2023
    2023
    Citations: 1
  • Modeling and simulation of terahertz detectors Based on mercury cadmium telluride
    V Devarakonda
    IIT (BHU) Varanasi , 2022
    2022
  • Enhanced optoelectronic properties of a mercury cadmium telluride based double heterojunction photodetector for terahertz applications
    V Devarakonda, A Pandey, P Chakrabarti
    Optik 247, 167947 , 2021
    2021
    Citations: 10
  • Performance analysis of N+-C d T e/n 0-Hg 0.824675 Cd 0.175325 T e/p+-Hg 0.824675 Cd 0.175325 T en-i-p photodetector operating at 30 μm wavelength for terahertz applications
    V Devarakonda, ADD Dwivedi, A Pandey, P Chakrabarti
    Optical and Quantum Electronics 52 (7), 340 , 2020
    2020
    Citations: 9
  • Training time and memory reduction algorithms for Speaker Recognition
    PRK Rao, DV Kumar, YS Rao
    2012 NATIONAL CONFERENCE ON COMPUTING AND COMMUNICATION SYSTEMS, 1-6 , 2012
    2012
  • Principal factor analysis and SVM based effective speaker recognition
    PRK Rao, YS Rao, DV Kumar
    2012 Third International Conference on Computing, Communication and … , 2012
    2012
    Citations: 1

MOST CITED SCHOLAR PUBLICATIONS

  • Enhanced optoelectronic properties of a mercury cadmium telluride based double heterojunction photodetector for terahertz applications
    V Devarakonda, A Pandey, P Chakrabarti
    Optik 247, 167947 , 2021
    2021
    Citations: 10
  • Performance analysis of N+-C d T e/n 0-Hg 0.824675 Cd 0.175325 T e/p+-Hg 0.824675 Cd 0.175325 T en-i-p photodetector operating at 30 μm wavelength for terahertz applications
    V Devarakonda, ADD Dwivedi, A Pandey, P Chakrabarti
    Optical and Quantum Electronics 52 (7), 340 , 2020
    2020
    Citations: 9
  • A proposed graphene-gated semiconductor terahertz detector
    V Devarakonda, A Pandey, P Chakrabarti
    Optik 288, 171204 , 2023
    2023
    Citations: 1
  • Principal factor analysis and SVM based effective speaker recognition
    PRK Rao, YS Rao, DV Kumar
    2012 Third International Conference on Computing, Communication and … , 2012
    2012
    Citations: 1
  • Implementation of Digital Logic Gate Families Using Low Operating Flexible Organic TFT Based on Innovative Compact Modeling Approach
    MS Mehrolia, AK Mishra, R Singh, S Yadav, V Devarakonda, AK Singh
    2025 3rd IEEE International Conference on Industrial Electronics … , 2025
    2025
  • CAM Based With-Memory Computing for ALU Operations
    CS Vardhan, BNH Nandan, PT Kumar, NT Krishna, R Peesapati, ...
    2024 IEEE 21st India Council International Conference (INDICON), 1-6 , 2024
    2024
  • DLP Based Processing-in-Memory Architecture Leveraging Content Addressable Memory
    CS Vardhan, BNH Nandan, PT Kumar, NT Krishna, R Peesapati, ...
    2024 IEEE 8th International Conference on Information and Communication … , 2024
    2024
  • Modeling and simulation of terahertz detectors Based on mercury cadmium telluride
    V Devarakonda
    IIT (BHU) Varanasi , 2022
    2022
  • Training time and memory reduction algorithms for Speaker Recognition
    PRK Rao, DV Kumar, YS Rao
    2012 NATIONAL CONFERENCE ON COMPUTING AND COMMUNICATION SYSTEMS, 1-6 , 2012
    2012