Comprehensive Performance Study of Hashing Functions G. M. Sridevi, Medahalli Ramakrishna, DV Ashoka Computer Science Journal of Moldova, 2023 Most literature on hashing functions speaks in terms of hashing functions being either ‘good’ or ‘bad’. In this paper, we demonstrate how a hashing function that gives good results for one key set, performs badly for another. We also demonstrate that, for a single key set, we can find hashing functions that hash the keys with varying performances ranging from perfect to worst distributions. We present a study on the effect of changing the prime number ‘$p$’ on the performance of a hashing function from $H_1$ Class of Universal Hashing Functions. This paper then explores a way to characterize hashing functions by studying their performance over all subsets of a chosen Universe. We compare the performance of some popular hashing functions based on the average search performance and the number of perfect and worst-case distributions over different key sets chosen from a Universe. The experimental results show that the division-remainder method provides the best distribution for most key sets of the Universe when compared to other hashing functions including functions from $H_1$ Class of Universal Hashing Functions.
Partial Pseudo-Random Hashing for Transactional Memory Read/Write Data Processing and Validation G M Sridevi, Ashoka D V, B V Ajay Prakash Karbala International Journal of Modern Science, 2022 Development of a bypass parallel processing block is one of the emerging and interesting research areas in memory read/write application domain. Many Random Number Generation (RNG) techniques have been introduced for processing the data in storage memory. But the limitations include reduced efficiency, increased computational complexity, high area consumption and higher cost. This paper presents a novel dynamic memory register with optimal XOR design based on partial pseudo-random hashing to process transactional memory read/write data. Transfer characteristics of the current are analysed based on the pseudo differential pair for proficient memory utilization. A memory window is then created and adjusted for obtaining an optimal power flow with lesser data loss. The performance of the proposed design is evaluated using different performance measures. The power consumed for processing the data using the proposed design is reduced to nearly 25% when compared to other proposed designs along with reduced component usage. Delay is reduced to 2.31ns and a 15% improvement in frequency and nearly 4% increase in throughput is seen when compared to existing methods.