Subhash Chander Dubey

@gcetjammu.org.in

Associate Professor , Department of Electronics & Communication
Govt.College of Engineering and Technology, Jammu

Subhash Chander Dubey


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https://researchid.co/subrag11121gmail.com

RESEARCH INTERESTS

Micro Electronics, Low Power VLSI design, FPGA based digital design, Digital Controller design, FPGA based Controller Design, FPGA Based DPWM Design, DC-DC Converters for Low Voltage Applications, Topologies and their Control
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Scopus Publications

Scopus Publications

  • Performance evaluation and direction of arrival estimation in diverse beamforming approaches for enhanced signal reception in wireless communication systems
    Zareena Amin, Naresh Kumar, Subhash Chander Dubey
    International Journal of Wireless and Mobile Computing, 2024
    The 5G technology has revolutionised the tech, delivering Gigabits per second speed. To fulfil the data demands of end-users seamlessly, advanced signal processing techniques have been implemented, such as zero forcing, diversity implementation, beamforming, etc. This article offers a comparative assessment of beamforming algorithms, including Minimum Variance Distortionless Response (MVDR), Beamscan, Multiple Signal Classification (MuSiC) and Linearly Constrained Minimum Variance (LCMV). The evaluation revolves around the Direction of Arrival (DoA) estimation for incoming signals, conducted under realistic conditions. Among the algorithms under scrutiny, the MuSiC algorithm exhibits superior performance. Therefore, we extend the scope of the discussion by including an in-depth analysis on the error performance of the MuSiC algorithm. Different factors that can impact the accuracy of the estimating procedure have been considered. Results depict that Signal-to-Noise ratio, Snapshot count and Array size positively correlate with estimation accuracy. Also, for coherent signals, an enhanced MuSiC algorithm is presented.
  • 1×2 Pentagonal Patch Antenna Array Based Pancreatic Cancer Detection
    Gagandeep Kaur, Kushmanda Saurav, Subhash Chander Dubey
    Apscon 2024 2024 IEEE Applied Sensing Conference Proceedings, 2024
    This paper introduces a microwave technique to diagnose pancreatic cancer (PC) through a $1\\times 2$ pentagonal patch antenna array. A pancreatic phantom consisting of pancreas, liver, kidney, spleen, adrenal glands, gall bladder, ureter, muscle, fat, and skin is used with the antenna array. The operating band of the array lies within the frequency range of 2.13-2.21 GHz. The PC is studied by the introduction of a tumor in the phantom model of a healthy pancreas. It is observed that the tumor causes a shift in the resonance frequency of the antenna. The parameters of the antenna array are studied without and with tumor. A tumor’s presence results in an enhancement in reflection (VSWR), and an increase in E-field and gain of the antenna array. The Specific absorption rate (SAR) is below 2 W/Kg (for 10g), which is well within the safety limits. The current work provides a simple PC diagnosis technique that is fast, safe, compact, economical, comfortable, and non-invasive.
  • Parallel-Series Diode-based Ring Amplifier for Switched Capacitor Circuits
    Zainubia, Bipul Kumar Singh, Manish Pundir, Subhash Chander Dubey, Ambika Prasad Shah
    Proceedings of the IEEE International Conference on VLSI Design, 2024
    In this paper, a new ring amplifier architecture is proposed. The new architecture uses a parallel-series diode-connected resistor in place of a resistor in the second stage of the conventional self-biased ring amplifier. The settling time, dead zone voltage, and output voltage of the ring amplifier all are improved to a great extent. The proposed modification is implemented and verified using simulations in Cadence Virtuoso with 45nm industry standard CMOS technology. The simulation results demonstrate that the modified ring amplifier achieves a settling time of 3.51 ns and the dead zone voltage is 998.60 mV which is $0.54 \\times$ and $1.21 \\times$ than that of the conventional self-biased ring amplifier. 2000 Monte Carlo simulations on settling time show the proposed circuit is robust against the process variations and has minimum deviation.
  • A Circularly Polarized Antenna Array Based Pancreatic Cancer Detection
    Gagandeep Kaur, Kushmanda Saurav, Subhash Chander Dubey
    2023 IEEE Microwaves Antennas and Propagation Conference Mapcon 2023, 2023
    This paper introduces a microwave technique to diagnose pancreatic cancer (PC) through a $2 \\times 2$ sequentially rotated circularly polarized (CP) patch antenna array. A pancreatic phantom consisting of pancreas, liver, kidney, spleen, muscle, fat, skin, etc. is used with the antenna array. The operating band of the array lies within the frequency range of 1.5-2.2 GHz. The PC is studied by introduction of tumor in the phantom model of a healthy pancreas. It is observed that the tumor causes a shift in the resonance frequency of the antenna. The parameters of antenna array is studied for the four stages of PC depending upon the tumor size in each stage. The increase in the size of tumor causes an enhancement in reflection, an increase in E/H-field and a decrease in axial ratio of the antenna array. The Specific absorption rate (SAR) for the different stages of PC is below 2 W/Kg for 10g, which is well within the safety limits. The current work provides a simple PC diagnosis technique which is fast, safe, compact, economical, comfortable and non-invasive.
  • Investigation of Adaptive Beam-forming Algorithms for Smart Antennas System
    Simrandeep Kaur, Naresh Kumar, Subhash Dubey
    Iop Conference Series Materials Science and Engineering, 2021
    Smart antennas are examined as a promising technology in wireless communication systems. In the development of smart antenna technology, Adaptive beam-forming is the most important aspect. Adaptive beam-forming uses various algorithms to identify the signals in the desired direction and separate the interference from the undesired/unwanted direction. In this paper, Proposed Adaptive Beam-forming Algorithm offers the better solution for reducing interference and improves the system capacity. The main objective of this paper is to analyze the different approaches used for designing the smart antennas to track the desired signal and put perfect null towards the interferer signal.
  • ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: A review
    Subhash Chander, Pramod Agarwal, Indra Gupta
    Central European Journal of Engineering, 2013
    Pulse width modulation (PWM) has been widely used in power converter control. This paper presents a review of architectures of the Digital Pulse Width Modulators (DPWM) targeting digital control of switching DC-DC converters. An attempt is made to review the reported architectures with emphasis on the ASIC and FPGA implementations in single phase and single-output DC-DC converters. Recent architectures using FPGA’s advanced resources for achieving the resolution higher than classical methods have also been discussed. The merits and demerits of different architectures, and their relative comparative performance, are also presented. The Authors intention is to uncover the groundwork and the related references through this review for the benefit of readers and researchers targeting different DPWM architectures for the DC-DC converters.
  • Design and implementation of field programmable gate array based Digital Pulse Width Modulator for Synchronous buck converter
    Subhash Chander, Pramod Agarwal, Indra Gupta
    Journal of Low Power Electronics, 2012
  • Auto-tuned, discrete PID controller for DC-DC converter for fast transient response
    Subhash Chander, Pramod Agarwal, Indra Gupta
    India International Conference on Power Electronics Iicpe 2010, 2011
    Ziegler-Nichols tuned PID controller's performances usually are not acceptable for applications requiring precise control. In this paper an improved discrete auto-tuning PID scheme is developed for DC-DC converters where large load changes are expected or the need for fast response time. The algorithm developed in this paper is used for the tuning discrete PID controller to obtain its parameters with a minimum computing complexity and is applied to Synchronous buck converter to improve its performance. To improve the transient response and rise time of the Converter, the controller parameters are continuously modified based on the current process trend. For its implementation a synchronous buck converter is designed and its MATLAB/Simulink model with non-linear parameters is developed and considered. Also, the non-linear effects such as S/H, quantization, delay, and saturation are considered in the close loop model. The simulation results demonstrate the effectiveness of the developed algorithms.
  • Tightly regulated single input, triple-output (SITO) synchronous DC-DC converter for low voltage applications
    International Review on Modelling and Simulations, 2011
  • Design, modeling and simulation of DC-DC converter for low voltage applications
    Subhash Chander, Pramod Agarwal, Indra Gupta
    2010 IEEE International Conference on Sustainable Energy Technologies Icset 2010, 2010
    This paper presents design, modeling and simulation of a low-power digitally controlled synchronous rectifier (SR) buck converter. Due importance is given in the model to the effect of non-linear parameters in low voltage converters, such as equivalent series resistance ESL of the inductor, ESR of capacitor and RDS(on) of MOSFET switches. A digital PID controller is design adopting direct digital design approach, further to improve its transient response the design is modified to achieve Auto-tuned discrete PID Controller (AT-PID).The performances of two controllers are compared. Simulations of a digital control synchronous buck are performed with Matlab/Simulink. The simulation results show that the approach enables high-speed dynamic performance.
  • Design, modeling and simulation of DC-DC converter
    Subhash Chander, Pramod Agarwal, Indra Gupta
    2010 9th International Power and Energy Conference IPEC 2010, 2010
  • FPGA-based PID controller for DC-DC converter
    Subhash Chander, Pra mod Agarwal, Indra Gupta
    2010 Joint International Conference on Power Electronics Drives and Energy Systems Pedes 2010 and 2010 Power India, 2010
  • Design, modeling and simulation of point of load converter (niPOL)
    Ecti Con 2010 the 2010 Ecti International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology, 2010