Vikas Ambekar

@tkrcet.ac.in

Associate Professor, Dept of ECE
TKR college of Engineering and Technology

Vikas Ambekar


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https://researchid.co/vikas434

EDUCATION

PhD from NIT Patna in VLSI (2024)

RESEARCH, TEACHING, or OTHER INTERESTS

Engineering, Electronic, Optical and Magnetic Materials
5

Scopus Publications

29

Scholar Citations

3

Scholar h-index

1

Scholar i10-index

Scopus Publications

  • Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates
    Vikas Ambekar, A. Theja, Meena Panchore, Chithraja Rajan, Bhumika Neole
    International Journal of Numerical Modelling Electronic Networks Devices and Fields, 2025
    The objective of this study is to examine how interface trap charges (ITC) influence the logic performance of a p‐type heterojunction vertical TFET structure without and with gate overlap (HJVTFET‐WOG and HJVTFET‐WG). The logic gates can be realized with the help of the HJ‐VTFET that uses germanium as the source material. Using HJVTFET‐WOG and HJVTFET‐WG structures, our simulations have proven that two‐input universal logic functions like NAND and NOR gates may be realized. By adjusting the gate‐source overlap region and choosing the right silicon body thickness, the suggested vertical TFET is able to perform logic operations. For verifying the universal gate functionality, the HJVTFET drain current characteristic and energy band diagram are analyzed by considering the effect of trapped charges. The tunneling width of logic functions is narrower when the ITC is positive and wider when it is negative, and the effective sub‐threshold slopes (SS) have been examined. It has been discovered that positive ITCs can enhance device capabilities, while negative ITCs lead to diminishing functionality. The suggested HJVTFET‐WOG structure is a promising structure for implementing the logic gates for digital application under the influence of interface trap charges because its electrical performance is less vulnerable to ITC than HJVTFET‐WG.
  • High-Selectivity-Based Novel Split-Gate VTFET Biosensor for Identification of SARS-CoV-2
    A. Theja, Vikas Ambekar, Meena Panchore
    Ecs Journal of Solid State Science and Technology, 2024
    The World Health Organization (WHO) has officially declared the international outbreak of severe acute respiratory syndrome coronavirus-2 (SARS-CoV-2), often known as Coronavirus Disease 2019 (COVID-19), a global pandemic based on the significant and sudden increase in human infections worldwide. With suitable treatment and early diagnosis, this outbreak can be controlled to a certain extent. In the present research, the performance of a novel dielectrically modulated heterojunction-based splitgate double cavity vertical TFET biosensor for detecting SARS-CoV-2 with reference to the virus spike, DNA and envelope proteins has been thoroughly investigated. The suggested sensor’s sensitivity has been evaluated through the computation of the deviation in drain current. We model the hybridized biomolecules in the nanogaps as the dielectric constant equivalent of the viral proteins. Additionally, sensing speed and selectivity analysis pertaining to the various biomolecules are also investigated. The proposed sensor exhibits a notably high sensitivity (on the order of 108), high sensing speed, and high selectivity (on the order of 106), indicating its potential as a superior sensor. This study also examines the influence of variations in DNA charge density on the performance of the device. Ultimately, the proposed sensor is evaluated in comparison to its sensitivity and selectivity of a variety of FET-based biosensors previously documented in the literature.
  • Effect of ITC on Boolean functionality of n-type heterojunction vertical TFETs
    Vikas Ambekar, Meena Panchore
    Microelectronics Journal, 2023
  • Realization of high-speed logic functions using heterojunction vertical TFET
    Vikas Ambekar, Meena Panchore
    Applied Physics A Materials Science and Processing, 2023
  • Realization of Boolean Functions Using Heterojunction Tunnel FETs
    Vikas Ambekar, Meena Panchore
    Silicon, 2022

RECENT SCHOLAR PUBLICATIONS

  • Design of an Efficient Traffic Light Control System Using Verilog HDL
    KR Krishna, K Prem, B Vani, A Theja, A Vikas
    2025 5th International Conference on Artificial Intelligence and Signal … , 2025
    2025
  • Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates
    V Ambekar, A Theja, M Panchore, C Rajan, B Neole
    International Journal of Numerical Modelling: Electronic Networks, Devices … , 2025
    2025
  • High-selectivity-based novel split-gate VTFET biosensor for identification of SARS-CoV-2
    A Theja, V Ambekar, M Panchore
    ECS Journal of Solid State Science and Technology 13 (3), 037003 , 2024
    2024
    Citations: 6
  • Effect of ITC on Boolean functionality of n-type heterojunction vertical TFETs
    V Ambekar, M Panchore
    Microelectronics Journal 142, 105988 , 2023
    2023
    Citations: 2
  • Gysel Power Divider Miniaturization Using an Inter-Digital Capacitor-Based Slow-Wave Structure
    M Kumar, A Kumar, P Sah, P Kumar, A Vikas, A Theja
    International Conference on Machine Vision and Augmented Intelligence, 159-167 , 2023
    2023
  • FinFET process technology for RF and millimeter wave applications
    A Theja, A Vikas, M Panchore, K Cecil
    RF Circuits for 5G Applications: Designing with mmWave Circuitry, 189-221 , 2023
    2023
    Citations: 1
  • Realization of high-speed logic functions using heterojunction vertical TFET
    V Ambekar, M Panchore
    Applied Physics. A, Materials Science & Processing 129 (3), 166 , 2023
    2023
    Citations: 11
  • Realization of Boolean functions using heterojunction tunnel FETs
    V Ambekar, M Panchore
    Silicon 14 (11), 6467-6475 , 2022
    2022
    Citations: 9

MOST CITED SCHOLAR PUBLICATIONS

  • Realization of high-speed logic functions using heterojunction vertical TFET
    V Ambekar, M Panchore
    Applied Physics. A, Materials Science & Processing 129 (3), 166 , 2023
    2023
    Citations: 11
  • Realization of Boolean functions using heterojunction tunnel FETs
    V Ambekar, M Panchore
    Silicon 14 (11), 6467-6475 , 2022
    2022
    Citations: 9
  • High-selectivity-based novel split-gate VTFET biosensor for identification of SARS-CoV-2
    A Theja, V Ambekar, M Panchore
    ECS Journal of Solid State Science and Technology 13 (3), 037003 , 2024
    2024
    Citations: 6
  • Effect of ITC on Boolean functionality of n-type heterojunction vertical TFETs
    V Ambekar, M Panchore
    Microelectronics Journal 142, 105988 , 2023
    2023
    Citations: 2
  • FinFET process technology for RF and millimeter wave applications
    A Theja, A Vikas, M Panchore, K Cecil
    RF Circuits for 5G Applications: Designing with mmWave Circuitry, 189-221 , 2023
    2023
    Citations: 1
  • Design of an Efficient Traffic Light Control System Using Verilog HDL
    KR Krishna, K Prem, B Vani, A Theja, A Vikas
    2025 5th International Conference on Artificial Intelligence and Signal … , 2025
    2025
  • Investigation of ITC Impact on Negative Bias HJVTFET for Implementing Universal Logic Gates
    V Ambekar, A Theja, M Panchore, C Rajan, B Neole
    International Journal of Numerical Modelling: Electronic Networks, Devices … , 2025
    2025
  • Gysel Power Divider Miniaturization Using an Inter-Digital Capacitor-Based Slow-Wave Structure
    M Kumar, A Kumar, P Sah, P Kumar, A Vikas, A Theja
    International Conference on Machine Vision and Augmented Intelligence, 159-167 , 2023
    2023