Narayan A.Badiger

@sgbit.edu.in

Assistant Professor and E&C Dept.
S G Balekundri Institute of Technology

Narayan A.Badiger


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https://researchid.co/narayanab

EDUCATION

M.Tech (PhD)

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering
4

Scopus Publications

21

Scholar Citations

3

Scholar h-index

1

Scholar i10-index

Scopus Publications

  • Fin-FET Enabled High-Speed PLL Design for Low Power Applications
    Narayan A. Badiger, Sridhar Iyer
    IETE Journal of Research, 2025
    There have been enormous improvements in the performance of transistors in Complementary Metal Oxide Semiconductor (CMOS) technology by reducing the device dimensions. However, there are several challenges, including short channel effects (SCE), drain-induced barrier lowering (DIBL), leakage current, etc., which are related to CMOS scaling. The Fin- (Field Effect Transistor) FET technology is an assuring technique to face these problems since, with scaling down of the technology, Fin-FET provides enhanced electrostatic control through the channel in comparison to the planar CMOS transistor. In this work, a Phase Lock Loop (PLL) design implemented using Fin-FET in the shorted gate mode is proposed. The proposed work is simulated using the Spectre of Cadence tool with 18 nm Fin-FET technology considering a 0.8 V power supply at an operating frequency of 500 MHz. The obtained results show that in comparison to an existing CMOS-based 18 nm technology, the proposed Fin-FET-based PLL at 18 nm performs better by demonstrating (i) a faster lock time of 20.88 ns, (ii) output frequency ranging between 2.4 GHz to 4.2 GHz, and (iii) consuming smaller area by using lesser numbers of transistors thereby incurring lesser power dissipation of 75.27 µW. Overall, the consequence of this study demonstrates that Fin-FET devices exhibit excellent short-channel behavior, have significantly lower switching times, and have a high current density in comparison with the MOSFET technology.
  • Design & Implementation of High Speed and Low Power PLL Using GPDK 45 nm Technology
    Narayan A. Badiger, Sridhar Iyer
    Journal of the Institution of Engineers India Series B, 2024
  • Design of Phase Frequency Detector for Low Power PLL Using GPDK 45nm Technology
    Narayan A. Badiger, Sridhar Iyer
    2023 International Conference on Network Multimedia and Information Technology Nmitcon 2023, 2023
    A key component in Phase-Locked Loop (PLL) circuits is Phase-Frequency Detectors (PFD), which find applications in numerous high-speed applications like processors and communication systems. The objective of this article is to design a PFD to (i) overcome the issue of high power dissipation and (ii) reduce the area of the existing design. A Cadence Virtuoso environment is used to design a proposed PFD and is implemented using Generic Process Development Kit (GPDK) 45 nm technology with a supply voltage of 1V. The outcomes represent that the proposed PFD consumes a power of 66.25 nw, which is considerably lower than the existing designs. And also, the proposed PFD is designed using 10 transistors which reduce the area in comparison to the convention of using 16 transistors or more.
  • Power and Delay Analysis of a CMOS Inverter
    Narayan A. Badiger, Sridhar Iyer, Sujay Gejji
    2023 International Conference on Data Science and Network Security Icdsns 2023, 2023
    The major challenge in designing and synthesizing VLSI circuits is to minimize propagation delay and Power Dissipation (Pd). This depends on the design parameters such as W/L ratio, scaling technology, and load capacitance. This paper focuses on detailed study of the propagation delay and dynamic power of a Complementary Metal Oxide Semiconductor (CMOS) inverter considering a channel length below 45nm following which, the best geometry for the minimum delay is found. For simulations, the standards of model parameters are used from the Berkeley Predictive Technology Model (PTM), and the study is performed for the technology including 16nm, 22nm, 32nm, 45nm with the help of the Electric software and LT Spice simulation tool. Our study shows that the CMOS inverter designed using the proposed methodology enhances the static and total power dissipation in comparison to the conventional design. The results demonstrate that a variation of the load capacitance leads to a change in the delay and dynamic power, and the technology scaling results in an increase of delay; however, with a decrease in the dynamic power values.

RECENT SCHOLAR PUBLICATIONS

  • Device Modeling and Performance Analysis of FinFETs for Advanced Technology Nodes Using TCAD
    NA Badiger
    2025
  • Fin-FET Enabled High-Speed PLL Design for Low Power Applications
    NA Badiger, S Iyer
    IETE Journal of Research 71 (5), 1614-1629 , 2025
    2025
  • Design & Implementation of High Speed and Low Power PLL Using GPDK 45 nm Technology
    NA Badiger, S Iyer
    Journal of The Institution of Engineers (India): Series B 105 (2), 239-249 , 2024
    2024
    Citations: 12
  • Design and Analysis of 6T SRAM using 45 nm gpdk Technology
    AK Prof. Narayan A.Badiger, Sneha Biradar
    International Conference on Recent Advances in Science Engineering … , 2024
    2024
  • Design of Phase Frequency Detector for Low Power PLL Using GPDK 45nm Technology
    NA Badiger, S Iyer
    2023 International Conference on Network, Multimedia and Information … , 2023
    2023
    Citations: 4
  • Power and Delay Analysis of a CMOS Inverter
    NA Badiger, S Iyer, S Gejji
    2023 IEEE International Conference on Data Science and Network Security … , 2023
    2023
    Citations: 1
  • Intelligent Night Surveillance Using Drone
    NAB Sainand Prabhu 1, Swati Hakare 2, Trupti Hawaldar 3, Vikas Madanashetti 4
    International Journal of Research Publication and Reviews 4 (5), 8 , 2023
    2023
  • Efficient Multi-Object Detecting Assistive System for Visually Impaired People
    NA Badiger
    Research Square (Research Square) , 2022
    2022
  • GSM Based Needleless Blood Glucose Monitoring System
    NA Badiger, P Borgave, NV Bevinakoppamath, V Chandrashekhar, ...
    2020
  • Lecture notes on Microwaves & Antenna
    P Narayan AB
    https://lecturenotes.in/notes/27785-antennas-and-microwave-engineering … , 2017
    2017
  • A Survey on Leakage Power Reduction Techniques
    MNA BADIGER, DRM KULKARNI
    International Journal of Emerging Technology in Computer Science … , 2015
    2015
  • Fpga implementation of image enhancement using verilog hdl
    NA Badiger, MJ Muragod, MP Pattar, M Priyanka
    algorithms 3 (12) , 2014
    2014
    Citations: 4

MOST CITED SCHOLAR PUBLICATIONS

  • Design & Implementation of High Speed and Low Power PLL Using GPDK 45 nm Technology
    NA Badiger, S Iyer
    Journal of The Institution of Engineers (India): Series B 105 (2), 239-249 , 2024
    2024
    Citations: 12
  • Design of Phase Frequency Detector for Low Power PLL Using GPDK 45nm Technology
    NA Badiger, S Iyer
    2023 International Conference on Network, Multimedia and Information … , 2023
    2023
    Citations: 4
  • Fpga implementation of image enhancement using verilog hdl
    NA Badiger, MJ Muragod, MP Pattar, M Priyanka
    algorithms 3 (12) , 2014
    2014
    Citations: 4
  • Power and Delay Analysis of a CMOS Inverter
    NA Badiger, S Iyer, S Gejji
    2023 IEEE International Conference on Data Science and Network Security … , 2023
    2023
    Citations: 1
  • Device Modeling and Performance Analysis of FinFETs for Advanced Technology Nodes Using TCAD
    NA Badiger
    2025
  • Fin-FET Enabled High-Speed PLL Design for Low Power Applications
    NA Badiger, S Iyer
    IETE Journal of Research 71 (5), 1614-1629 , 2025
    2025
  • Design and Analysis of 6T SRAM using 45 nm gpdk Technology
    AK Prof. Narayan A.Badiger, Sneha Biradar
    International Conference on Recent Advances in Science Engineering … , 2024
    2024
  • Intelligent Night Surveillance Using Drone
    NAB Sainand Prabhu 1, Swati Hakare 2, Trupti Hawaldar 3, Vikas Madanashetti 4
    International Journal of Research Publication and Reviews 4 (5), 8 , 2023
    2023
  • Efficient Multi-Object Detecting Assistive System for Visually Impaired People
    NA Badiger
    Research Square (Research Square) , 2022
    2022
  • GSM Based Needleless Blood Glucose Monitoring System
    NA Badiger, P Borgave, NV Bevinakoppamath, V Chandrashekhar, ...
    2020
  • Lecture notes on Microwaves & Antenna
    P Narayan AB
    https://lecturenotes.in/notes/27785-antennas-and-microwave-engineering … , 2017
    2017
  • A Survey on Leakage Power Reduction Techniques
    MNA BADIGER, DRM KULKARNI
    International Journal of Emerging Technology in Computer Science … , 2015
    2015