I am currently working as a postdoc research associate at IISc Bangalore, MSD’s Lab in the area of ESD effect
on semiconductor devices. Previously, I have worked as an Assistant Professor in KL University, Hyderabad
campus in the department of Electronics and Communication Engineering. I have completed Ph.D. under the
guidance of Prof. Shrish Verma and Dr. Alok Naugarhiya from the National Institute of Technology Raipur.
My area of research is Power Semiconductor Devices, more specifically worked on Insulated Gate Bipolar
Transistor. During my research work I have published 4 articles in SCI journals including one in IEEE Electron
Device Letters and one article in IEEE Transactions on Electron Devices. I have also worked as a Lab Engineer
at National Institute of Technology Raipur under Special Manpower Development Program Chip to System
Design (SMDP-C2SD) project. In this project, I have worked on Digital IC Design and have hands on experience
in FPGA design.
EDUCATION
Ph.D. (ECE, National Institute of Technology Raipur)
M.Tech. (VLSI System Technology, Shiv Nadar University)
B.E. (CSVTU, Bhilai)
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, Multidisciplinary
17
Scopus Publications
103
Scholar Citations
6
Scholar h-index
4
Scholar i10-index
Scopus Publications
Proposal to Achieve the Ultimate Holding Voltage Tunability in Silicon Controlled Rectifiers (SCRs) for a Wide Range of ESD Protection Application Mayank Yadav, Mahesh Vaidya, Mayank Shrivastava IEEE International Reliability Physics Symposium Proceedings, 2025 A novel silicon-controlled rectifier (SCR) concept for on chip ESD protection is proposed with holding voltage tunability from as low as 2V to the well breakdown voltage (10V). The novel proposal replaces the standard N+ and P+ implants in N-Tap/Cathode and P-Tap/Anode by P+-N+ implant and N+-P+ implants, respectively. Detailed physical insight of the proposed concept and several derivative concepts is given, explaining the trigger and holding voltage tunability. Besides, additional, rather refined, tunability is depicted by engineering the junction profile of the P+-N+ and N+-P+ implants. The proposed concept together with the junction profile engineering demonstrates the ultimate holding voltage tunability.
Novel Trigger Circuit & SCR Device Co-Engineering Based Local (I/O-VSS & I/O-VDD) ESD Clamp Concepts with Improved Latch-Up Susceptibility, Lower Leakage and Lower Capacitance for Ultra High Speed I/Os Mitesh Goyal, Mukesh Chaturvedi, Harihar Nath, Mahesh Vaidya, Mayank Shrivastava IEEE International Reliability Physics Symposium Proceedings, 2025 In this work, a novel silicon-controlled rectifier (SCR) based local protection concept is presented with co-engineered device and trigger circuit. This results in improved latch-up robustness, lower PAD capacitive loading and lower leakage when compared to the reference (state-of-the-art till date) concept. The proposed and reference concepts are realized in Samsung 28nm process for experimental validation and benchmarking. Its TLP/vf-TLP characteristics and other ESD measurement results along with the design trade-offs are presented and compared with the reference concept. A TCAD based device and circuit co-optimization (DTCO) methodology is also presented. The proposed concept can realize the demanding I/O needs of SCR based local clamps, qualified for HBM to CDM time domains, and meeting ESD specs required for high speed I/O buffers.
Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application Shriharsh Prasad Behera, Mahesh Vaidya, Alok Naugarhiya Proceedings of the IEEE International Conference on VLSI Design, 2024 This article explains about electrical behavior of new Insulated Gate Bipolar Transistor (IGBT) by providing stepped oxide pattern at gate terminal with splitting N-poly structure in to three verticals. In order to form a stepped oxide pattern the bottom oxide thickness of the gate decreases from left to right. On the right side, the bottom oxide is thinner than the channel side. Furthermore, the oxide thickness along the channel wall has been kept thinner which increases Gate to emitter charges (QGE) in comparison to conventional SJ-IGBT. These additional charges also lead to increase output current which helps to decrease area-specific on-resistance ($\\mathrm{R}_{\\text {on. }}$.A). However, reduced gate to collector charges $\\left(Q_{G C}\\right)$ is offered by increased bottom oxide thickness along the channel, which improves switching performance of the device and make it good candidate for high speed application. The collective advancement in $Q_{G E}$ and QGC enables fast switching and provide 67% reduced turn-off loss ($\\mathrm{E}_{\\text {off }}$). Additionally, in our study it is observed that modifiedworkfunction by replacing middle N-Poly with P-Poly reduces the peak electric field at the bottom side and enables 12% improvement in BV as compared to SJ-IGBT.
Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR Mitesh Goyal, Mukesh Chaturvedi, Raju Kumar, Mahesh Vaidya, Mayank Shrivastava IEEE International Reliability Physics Symposium Proceedings, 2024 In this work co-optimization of silicon-controlled rectifier (SCR) ESD characteristics with its low voltage trigger circuit is presented. Resistance and Capacitance (RC) controlled thick gate NMOS and PMOS based circuits have been explored and compared. The design approach is discussed and presented for low trigger SCR for two different trigger circuits. In the process we find that some of the trigger circuits previously reported in literature do not work as desired until co-optimized device engineering techniques are used. The circuit insights are explored using well calibrated electrothermal 3D process and device TCAD mixed mode simulations.
Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices Mitesh Goyal, Mukesh Chaturvedi, Raju Kumar, Mahesh Vaidya, Mayank Shrivastava IEEE International Reliability Physics Symposium Proceedings, 2024 In this paper physics of experimentally observed abnormal behavior in STI bounded Silicon-Controlled-Rectifier (SCR) structures is investigated and explained using basic principles and 3D electrothermal TCAD simulations. The SCR device is found to show pulse to pulse instability in the negative resistance (snapback) region during the lOOns pulse width TLP measurement. The instabilities were independent of SCR geometrical design variations but were dependent on the load line conditions used in the TLP measurement. The physical insights and device physics has been explored using well calibrated 3$D$ process and device TCAD.
Insulated Gate Bipolar Transistors with Deep Trench Technology for Low Loss Switching Application Alok Naugarhiya, Chumki Das, Mahesh Vaidya Proceedings of IEEE International Conference on Modelling Simulation and Intelligent Computing Mosicom 2023, 2023 A new insulated gate bipolar transistor (IGBT) with deep trench technology is proposed to improve on-state voltage drop (Von) and turn-off energy loss (Eoff) trade-off. The Deep trench gate IGBT (DT-IGBT) increases the charge carriers along the channel, leads to improve the collector current by 58% in comparison to conventional IGBT resulting reduction on Von. Apart from that, the collector section is segregated into two-parts, namely p-col and p−-col. The lower concentration of p−-col region creates a Schottky contact with metal and increases the recombination rate by reducing minority carrier lifetime. This effect allows the device to turn-off early and shows an advancement in turn-off time further reduces the Eoff by 33% in comparison to the conventional IGBT. The reduced doping in the collector region alter the electric field of the device and enhances the breakdown voltage (BV) by 7% with respect to the conventional one.
1.2 kV Stepped Oxide Trench Insulated Gate Bipolar Transistor with Low Loss for Fast Switching Application Mahesh Vaidya, Alok Naugarhiya, Shrish Verma, Guru Prasad Mishra Ecs Journal of Solid State Science and Technology, 2022 In this article, a gate engineering technique is used in Insulated gate bipolar transistor (IGBT) for fast switching applications. The modification consists of stepped oxide pattern at gate terminal with n-poly layer sandwiched between two p-poly layers. The oxide thickness increases from top to bottom so as to create a stepped structure. The oxide thickness is lesser on channel side and higher on collector side. The less thickness beside the channel increases gate to emitter charges (QGE) by extracting extra charges along the channel. The presence of these extra charges also increases the collector current density resulting reduction in the area specific on-resistance (Ron.A). On the other hand, the higher thickness at the bottom side of gate offers reduction in gate to collector charges (QGC). Furthermore, to elongate the impact of QGC reduction, the low doped p-col region has been facilitated which also play an important role to increase the breakdown voltage by reducing corner electric field. This p-col region creates charge extraction path to swept out charges from the drift region while turn-off event and makes the device to turn-off quickly. The collective improvement in QGE and QGC provides fast switching to the proposed device by improving turn-off time by 63% and also reduces turn-off loss (Eoff) by 55% as compared to the conventional device. Furthermore, the change in the workfunction also provides the reduction of channel peak electric field and offers 10% increment in the BV as compared to the conventional IGBT.
Collector Engineered Bidirectional Insulated Gate Bipolar Transistor with Low Loss Mahesh Vaidya, Alok Naugarhiya, Shrish Verma, Guru Prasad Mishra IEEE Transactions on Electron Devices, 2022 The collector engineered bidirectional insulated gate bipolar transistor (CEB-IGBT) with p-buffer and semi-superjunction (Semi-SJ) is proposed. The structural modification at collector side provides support to reverse breakdown voltage (<inline-formula> <tex-math notation="LaTeX">$\\text {BV}_{R}$ </tex-math></inline-formula>) in two ways. First, the p-buffer layer allows the device to deplete completely and eliminates premature breakdown effects. Second, the Semi-SJ region introduces an electric field component in the <inline-formula> <tex-math notation="LaTeX">${x}$ </tex-math></inline-formula>-direction (<inline-formula> <tex-math notation="LaTeX">${E}_{X}$ </tex-math></inline-formula>) in order to further improve the <inline-formula> <tex-math notation="LaTeX">$\\text {BV}_{R}$ </tex-math></inline-formula>. The overall increased electric field, which is a resultant of <inline-formula> <tex-math notation="LaTeX">${E}_{X}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${E}_{Y}$ </tex-math></inline-formula>, improves <inline-formula> <tex-math notation="LaTeX">$\\text {BV}_{R}$ </tex-math></inline-formula> by 53.83% compared to nonpunchthrough IGBT (NPT-IGBT). The efficient potential distribution in the drift region provides support to forward breakdown (<inline-formula> <tex-math notation="LaTeX">$\\text {BV}_{F}$ </tex-math></inline-formula>) as well. The n-layer below p-body acts as a field stop (FS) layer, which reduces the leakage current during the OFF-state condition. The p-buffer, which injects higher minority charges along the drift side and n-layer with charge storage effect collectively, provides conductivity modulation in the epitaxial region in order to increase current handling capability. This high collector current density leads to reduce <inline-formula> <tex-math notation="LaTeX">${V}_{ \\mathrm{\\scriptscriptstyle ON}}$ </tex-math></inline-formula> by 14.5% compared to NPT-IGBT. Furthermore, the charge coupling effect of Semi-SJ region enables the proposed device to turn-off quickly with higher pillar doping and reduces turn-off loss (<inline-formula> <tex-math notation="LaTeX">${E}_{ \\mathrm{\\scriptscriptstyle OFF}}$ </tex-math></inline-formula>) in comparison with NPT-IGBT.
A low-loss variable-doped trench-insulated gate bipolar transistor with reduced on-state voltage Mahesh Vaidya, Alok Naugarhiya, Shrish Verma, Guru Prasad Mishra Semiconductor Science and Technology, 2021 The performance of a superjunction trench-insulated gate bipolar transistor with variable vertical doping in the epitaxial region along with variation in the collector layer is investigated. The concept of vertical variation transfers the avalanche multiplication point from the epitaxial edges to the middle of the pillar. The proposed device offers increased effective doping in the drift region, which reduces the on-state voltage ( Von ) without any degradation in the breakdown voltage. Furthermore, the horizontal doping variation in the collector layer supports the phenomenon in two ways: the left section of the collector layer reduces Von whereas the right portion enables an efficient discharging path, which allows improved switching performance. In addition to this, a reduction in the gate to collector charge ( QGC ) is observed because of the presence of a lightly doped n-region below the gate terminal. A two-dimensional numerical simulation revealed that the proposed device offers a 15.30% reduction in QGC compared with the conventional device. The structural modification offers a 40% reduction in turn-off time, resulting in a reduction in turn-off energy loss ( Eoff ).
High Speed Bootstrapping Generic Voltage Level Shifter Mahesh Vaidya, Alok Naugarhiya, Shrish Verma Proceedings of 2018 2nd International Conference on Advances in Electronics Computers and Communications Icaecc 2018, 2018
Novel trigger circuit & SCR device co-engineering based local (I/O-VSS & I/O-VDD) ESD clamp concepts with improved latch-up susceptibility, lower leakage and lower capacitance … M Goyal, M Chaturvedi, H Nath, M Vaidya, M Shrivastava 2025 IEEE International Reliability Physics Symposium (IRPS), 1-8 , 2025 2025 Citations: 4
Proposal to Achieve the Ultimate Holding Voltage Tunability in Silicon Controlled Rectifiers (SCRs) for a Wide Range of ESD Protection Application M Yadav, M Vaidya, M Shrivastava 2025 IEEE International Reliability Physics Symposium (IRPS), 1-5 , 2025 2025
Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR M Goyal, M Chaturvedi, R Kumar, M Vaidya, M Shrivastava 2024 IEEE International Reliability Physics Symposium (IRPS), 1-6 , 2024 2024 Citations: 4
Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices M Goyal, M Chaturvedi, R Kumar, M Vaidya, M Shrivastava 2024 IEEE International Reliability Physics Symposium (IRPS), 1-6 , 2024 2024 Citations: 4
Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application SP Behera, M Vaidya, A Naugarhiya 2024 37th International Conference on VLSI Design and 2024 23rd … , 2024 2024 Citations: 1
Insulated Gate Bipolar Transistors with Deep Trench Technology for Low Loss Switching Application A Naugarhiya, C Das, M Vaidya 2023 International Conference on Modeling, Simulation & Intelligent … , 2023 2023
1.2 kV Stepped Oxide Trench Insulated Gate Bipolar Transistor with Low Loss for Fast Switching Application M Vaidya, A Naugarhiya, S Verma, GP Mishra ECS Journal of Solid State Science and Technology 11 (11), 111008 , 2022 2022 Citations: 3
Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application M Vaidya, A Naugarhiya, S Verma, GP Mishra International Symposium on VLSI Design and Test, 53-64 , 2022 2022
Collector Engineered Bidirectional Insulated Gate Bipolar Transistor With Low Loss M Vaidya, A Naugarhiya, S Verma, GP Mishra IEEE Transactions on Electron Devices 69 (3), 1604-1607 , 2022 2022 Citations: 8
Design And Analysis Of Trench Superjunction Insulated Gate Bipolar Transistor Limitations And Solutions M Vaidya Raipur , 2022 2022
A low-loss variable-doped trench-insulated gate bipolar transistor with reduced on-state voltage M Vaidya, A Naugarhiya, S Verma, G Prasad Mishra Semiconductor Science and Technology 36 (7), 075002 , 2021 2021 Citations: 3
Lateral variation doped wide bottom trench gate IGBT for reduced on-resistance with improved gate charge M Vaidya, A Naugarhiya, S Verma Materials Today: Proceedings 46, 4587-4592 , 2021 2021
Lateral variation-doped insulated gate bipolar transistor for low on-state voltage with low loss M Vaidya, A Naugarhiya, S Verma, GP Mishra IEEE Electron Device Letters 41 (6), 888-891 , 2020 2020 Citations: 11
An eyewear adapted for defogging during surgery A Dixit, N Nagarkar, M, A Nagarkar, R Tripathi, A Gupta, M Vaidya WO Patent 2020136670A1 , 2020 2020
Trench IGBT with stepped doped collector for low energy loss M Vaidya, A Naugarhiya, S Verma Semiconductor Science and Technology 35 (2), 025015 , 2020 2020 Citations: 12
Design and Analysis of Improved IGBT with Embedded p + in N-Buffer Layer M Vaidya, A Naugarhiya, S Verma 2019 IEEE 16th India Council International Conference (INDICON), 1-4 , 2019 2019 Citations: 1
An Efficient Hardware Architecture for Route Discovery in AODV for a Sensor Node S Hafizullah, S Verma, M Vaidya, A Naugarhiya 9th Annual Information Technology, Electromechanical Engineering and … , 2019 2019 Citations: 2
A HAND HELD AUDIOMETER DEVICE AND METHOD THEREOF A Dixit, N Nagarkar, M, A Nagarkar, K Kumar, A Gupta, M Vaidya IN Patent 355,932 , 2018 2018
High speed bootstrapping generic voltage level shifter M Vaidya, A Naugarhiya, S Verma 2018 Second International Conference on Advances in Electronics, Computers … , 2018 2018 Citations: 7
SENSOR ENABLED DYNAMICALLY CONTROLLABLE WALKER SYSTEM R Kumar, A Dixit, K Kumar, M Vaidya, S Verma IN Patent 413,315 , 2017 2017
MOST CITED SCHOLAR PUBLICATIONS
Feature level fusion of palm print and fingerprint modalities using Discrete Cosine Transform A Gupta, E Walia, M Vaidya 2014 International Conference on Advances in Engineering & Technology … , 2014 2014 Citations: 21
Data compression using Shannon-fano algorithm implemented by VHDL M Vaidya, ES Walia, A Gupta 2014 International Conference on Advances in Engineering & Technology … , 2014 2014 Citations: 20
Trench IGBT with stepped doped collector for low energy loss M Vaidya, A Naugarhiya, S Verma Semiconductor Science and Technology 35 (2), 025015 , 2020 2020 Citations: 12
Lateral variation-doped insulated gate bipolar transistor for low on-state voltage with low loss M Vaidya, A Naugarhiya, S Verma, GP Mishra IEEE Electron Device Letters 41 (6), 888-891 , 2020 2020 Citations: 11
Collector Engineered Bidirectional Insulated Gate Bipolar Transistor With Low Loss M Vaidya, A Naugarhiya, S Verma, GP Mishra IEEE Transactions on Electron Devices 69 (3), 1604-1607 , 2022 2022 Citations: 8
High speed bootstrapping generic voltage level shifter M Vaidya, A Naugarhiya, S Verma 2018 Second International Conference on Advances in Electronics, Computers … , 2018 2018 Citations: 7
Novel trigger circuit & SCR device co-engineering based local (I/O-VSS & I/O-VDD) ESD clamp concepts with improved latch-up susceptibility, lower leakage and lower capacitance … M Goyal, M Chaturvedi, H Nath, M Vaidya, M Shrivastava 2025 IEEE International Reliability Physics Symposium (IRPS), 1-8 , 2025 2025 Citations: 4
Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR M Goyal, M Chaturvedi, R Kumar, M Vaidya, M Shrivastava 2024 IEEE International Reliability Physics Symposium (IRPS), 1-6 , 2024 2024 Citations: 4
Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices M Goyal, M Chaturvedi, R Kumar, M Vaidya, M Shrivastava 2024 IEEE International Reliability Physics Symposium (IRPS), 1-6 , 2024 2024 Citations: 4
1.2 kV Stepped Oxide Trench Insulated Gate Bipolar Transistor with Low Loss for Fast Switching Application M Vaidya, A Naugarhiya, S Verma, GP Mishra ECS Journal of Solid State Science and Technology 11 (11), 111008 , 2022 2022 Citations: 3
A low-loss variable-doped trench-insulated gate bipolar transistor with reduced on-state voltage M Vaidya, A Naugarhiya, S Verma, G Prasad Mishra Semiconductor Science and Technology 36 (7), 075002 , 2021 2021 Citations: 3
An Efficient Hardware Architecture for Route Discovery in AODV for a Sensor Node S Hafizullah, S Verma, M Vaidya, A Naugarhiya 9th Annual Information Technology, Electromechanical Engineering and … , 2019 2019 Citations: 2
Slotted CSMA/CA Simulation in Verilog A Chakradhari, S Tamrakar, R Basant, M Vaidya, S Majumdar, ... International Workshop in Internet of Things and TV White Spaces , 2017 2017 Citations: 2
Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application SP Behera, M Vaidya, A Naugarhiya 2024 37th International Conference on VLSI Design and 2024 23rd … , 2024 2024 Citations: 1
Design and Analysis of Improved IGBT with Embedded p + in N-Buffer Layer M Vaidya, A Naugarhiya, S Verma 2019 IEEE 16th India Council International Conference (INDICON), 1-4 , 2019 2019 Citations: 1
Proposal to Achieve the Ultimate Holding Voltage Tunability in Silicon Controlled Rectifiers (SCRs) for a Wide Range of ESD Protection Application M Yadav, M Vaidya, M Shrivastava 2025 IEEE International Reliability Physics Symposium (IRPS), 1-5 , 2025 2025
Insulated Gate Bipolar Transistors with Deep Trench Technology for Low Loss Switching Application A Naugarhiya, C Das, M Vaidya 2023 International Conference on Modeling, Simulation & Intelligent … , 2023 2023
Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application M Vaidya, A Naugarhiya, S Verma, GP Mishra International Symposium on VLSI Design and Test, 53-64 , 2022 2022
Design And Analysis Of Trench Superjunction Insulated Gate Bipolar Transistor Limitations And Solutions M Vaidya Raipur , 2022 2022
Lateral variation doped wide bottom trench gate IGBT for reduced on-resistance with improved gate charge M Vaidya, A Naugarhiya, S Verma Materials Today: Proceedings 46, 4587-4592 , 2021 2021
