Harshit Kansal

@harshitk@iiserb.ac.in

Research Associate
indian institute of science education and research bhopal

Harshit Kansal


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https://researchid.co/harshitkansal6988

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering, Electrical and Electronic Engineering, Engineering
18

Scopus Publications

57

Scholar Citations

5

Scholar h-index

1

Scholar i10-index

Scopus Publications

  • A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing
    Harshit Kansal, Aditya Sankar Medury
    Semiconductor Science and Technology, 2024
    Dielectrically modulated (DM) negative capacitance field effect transistor (NCFET)-based label-free biosensors have emerged as promising devices for accurate detection of various biomolecules, where the sensitivity of DM architectures strongly depends on the sensing mechanism as well as on the size of the nanocavity. Therefore, to achieve higher sensitivity along with reduced fabrication complexity, we propose to utilize a pre-existing drain-side spacer region as a nanocavity, in a fully depleted silicon-on-insulator-based NCFET architecture. The ferroelectric (FE) layer in the metal-ferroelectric-insulator-semiconductor configuration meaningfully alters the impact of the drain’s electric field on the source-side electrostatics, which results in higher sensitivity. Having quantified the sensitivity of an FE-dielectric (FE-DE) gate-stack-based NCFET biosensor, we now propose to include a paraelectric (PE) layer between the FE and DE materials, thus modifying the gate stack from FE-DE to FE-PE-DE with an equivalent negative capacitance seen from both stacks; here, a remarkable improvement is seen in the FE-PE-DE gate-stack-based NCFET, with nearly identical linearity performance, as seen from the high Pearson’s coefficient value ( r 2 ⩾ 0.9). Therefore, to illustrate the efficacy of the proposed sensing mechanism and the modified gate stack (FE-PE-DE), DE constant ( k Bio ) values in the range of k Bio = 4.5 to k Bio = 75.99 are considered. Finally, the effect of scaling the channel length ( L g ) on the sensitivity of the FE-PE-DE NCFET device is shown, and a high value, particularly at lower permittivity, demonstrates the versatility and wide applicability of the proposed NCFET biosensor.
  • Algorithm for Calibrating Effective Mass Parameters to consider Quantum Confinement Effects in Ultra-Thin-Body Devices for Various Temperatures
    Nalin Vilochan Mishra, Harshit Kansal, Yogesh Dhote, Ravi Solanki, Aditya Sankar Medury
    Journal of Electronic Materials, 2023
  • Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices
    Nalin Vilochan Mishra, Harshit Kansal, Ravi Solanki, Aditya Sankar Medury
    Journal of Physics D Applied Physics, 2023
    The effect of quantum confinement has become significant in terms of its impact on the scalability and electrostatics of ultra-thin-body double-gate MOSFETs. In this paper, we present a simplified model to account for the effect of quantum confinement, considering the contribution of the ground-state and the first excited state of the conduction band, on the electron carrier concentration, which when incorporated into the 1-D Poisson’s equation, enables the determination of the electrostatic potential. We establish the accuracy of the proposed model, over a wide range of process and electrical parameters, through aggressively benchmarking the electrostatics parameters obtained from the proposed model with results from the sp 3 d 5 s ∗ tight-binding method (TBM), over a wide range of device temperatures. Furthermore, a simplified model for the integrated channel charge density is shown in the form of a diffusion layer charge where the thickness and potential of this layer, while being gate voltage dependent, enables the channel charge density obtained from the model to agree well with results from TBM. Through this physics based and accurate model for the integrated charge, a simplified understanding of the gate capacitance is shown as a series combination of the diffusion layer capacitance, strong-inversion capacitance and oxide capacitance, which includes the effects of structural confinement as well as charge confinement at low and high gate voltages, respectively.
  • Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance
    Harshit Kansal, Aditya Sankar Medury
    Microelectronics Journal, 2023
  • Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog performance
    Manas Pratap, Harshit Kansal, Aditya Sankar Medury
    Microelectronics Journal, 2023
  • The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET
    Harshit Kansal, Aditya Sankar Medury
    Silicon, 2023
  • Temperature Dependent Band Gap Correction Model Using Tight-Binding Approach for UTB Device Simulations
    Nalin Vilochan Mishra, Ravi Solanki, Harshit Kansal, Aditya Sankar Medury
    IEEE Transactions on Nanotechnology, 2023
    In order to accurately determine the electrostatics of Ultra-Thin-Body (UTB) devices, the semi-empirical tight-binding (TB) approach is widely used for calculating the channel thickness dependent band structure of any material at those temperatures where TB parameters are available (generally defined at 0 K and 300 K). In this work, we analyze the variation of band structure for Si, Ge, and GaAs over different channel thicknesses at 0 K and 300 K, and show that the band curvature at the band minima remains unchanged with temperature, while the band gap changes significantly and affects the channel electrostatics. Based on this finding, we propose an approach to simulate the electrostatics of UTB devices, at any temperature between 0 K and 300 K, using the band structure obtained at 0 K, along with a suitable channel thickness and temperature-dependent band gap correction. From the results obtained for the channel charge density, we show good agreement with band structure based simulation results, at 300 K, over a wide range of channel thicknesses, for Si, Ge, and GaAs, while also showing good agreement with TCAD simulation results, at a typical intermediate temperature of 150 K, thus highlighting the accuracy, simplicity and wide applicability of the proposed approach.
  • Improved analog performance of FDSOI based NCFET with a ferroelectric-paraelectric-dielectric gate stack
    Harshit Kansal, Aditya Sankar Medury
    Semiconductor Science and Technology, 2022
    With the superior analog/RF performance of planar device architectures such as fully depleted silicon-on-insulator (FDSOI) MOSFETs, it becomes important to investigate the impact of a ferroelectric material in the gate stack, resulting in negative capacitance (NC) behavior, on the device performance. In this work, through calibrating the FDSOI MOSFET (as the baseline device architecture) with experimental data, we compare the impact of ferroelectric–dielectric (FE–DE) and ferroelectric–paraelectric–dielectric (FE–PE–DE) gate stacks on the electrostatics of an NCFET device for a practically realisable metal–ferroelectric–insulator–semiconductor (MFIS) structure. A suitable thickness of the ferroelectric (FE) layer in the FE–DE stack and the maximum drain–source voltage ( V d s ) that can be applied (determining the power supply voltage), are identified so as to ensure that constraints such as no negative differential resistance (NDR) effects, threshold voltage ( V t h ), sub-threshold slope (SS) invariability with drain voltage variations and hysteresis-free behavior in transfer characteristics ( I d – V g s ) are all satisfied. From the thickness of the FE layer in the FE–DE stack, the thickness of the FE layer in the FE–PE–DE stack (PE layer thickness is fixed at 1 nm) is determined where with a thicker FE layer, we obtain similar capacitance from the FE–PE–DE gate stack to that obtained from the FE–DE stack, while meeting all the constraints applied to the FE–DE stack based NCFET, enabling determination of the power supply voltage. Through showing good SSs with reduced output conductance ( g d s ), resulting in improved dc gain ( g m g d s ) and improved linearity parameters ( g m 2 and g m 3 ) along with scaling of power supply, an FE–PE–DE stack shows better analog performance, with lower power consumption, compared to an FE–DE stack, for an FDSOI NCFET, at 14 nm gate length.
  • FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs
    Harshit Kansal, Aditya Sankar Medury
    Microelectronics Journal, 2022
  • Negative capacitance partially junction-less FET for hysteresis-free and improved analog performance
    Harshit Kansal, A. S. Medury
    Japanese Journal of Applied Physics, 2022
    Given the advantage of high transconductance (g m) at low gate voltages (V gs), seen in junction-less (JL) transistors, it becomes important to incorporate these advantages in conventional bulk MOSFETs which have thus far been used extensively for analog circuit applications. In this work, we propose a partially JL channel in a bulk MOSFET device, which when investigated for a metal-ferroelectric-insulator-semiconductor (MFIS) with negative capacitance field-effect transistor (NCFET) shows superior analog device performance, with improved scalability. Through technology computer aided design (TCAD)-based transient simulations, we identify an optimum and almost constant ferroelectric layer thickness for different gate lengths, which enables hysteresis-free behavior, along with reasonably steep sub-threshold slopes (SS), that meets international roadmap for devices and systems specifications. For this device, we then determine the maximum drain voltage, V ds, which ensures no drain-induced barrier raise effects, based on which improved transconductance generation efficiency (g m/I d), with minimal gate induced drain leakage is shown.
  • Hysteresis-free Behavior and Improved Performance of Negative Capacitance Optimized Bulk MOSFET
    Harshit Kansal, Aditya Sankar Medury
    2022 IEEE Silicon Nanoelectronics Workshop Snw 2022, 2022
  • Confinement Effect and Conduction Band Offset in DG-SOI MOSFETs: A Simulation Study
    Harshit Kansal, Nalin Vilochan Mishra, Aditya Sankar Medury
    Proceedings of the International Semiconductor Conference CAS, 2022
  • Comparison of Different Approaches used for Estimation of Electrostatics in UTB devices
    Nalin Vilochan Mishra, Harshit Kansal, Ravi Solanki, Aditya Sankar Medury
    Proceedings of the IEEE Conference on Nanotechnology, 2022
  • TCAD based Modeling of Sub-surface Leakage in Short Channel Bulk MOSFETs
    Harshit Kansal, Aditya Sankar Medury
    2021 Joint International Eurosoi Workshop and International Conference on Ultimate Integration on Silicon Eurosoi Ulis 2021, 2021
  • Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs
    Harshit Kansal, Aditya Sankar Medury
    Aip Advances, 2021
  • Towards Novel Channel Doping Profiles in Short Channel Bulk MOSFETs for OFF-State Current Reduction and Superior Channel Electrostatics
    Harshit Kansal, Aditya Sankar Medury
    2020 IEEE Silicon Nanoelectronics Workshop Snw 2020, 2020
  • Quantum confinement effects and electrostatics of planar nano-scale symmetric double-gate soi MOSFETs
    Aditya Sankar Medury, Harshit Kansal
    2019 IEEE International Conference on Electron Devices and Solid State Circuits Edssc 2019, 2019
  • Short-channel effects and sub-surface behavior in bulk MOSFETs and nanoscale DG-SOI- MOSFETs: A TCAD investigation
    Harshit Kansal, Aditya Sankar Medury
    2019 Silicon Nanoelectronics Workshop Snw 2019, 2019

RECENT SCHOLAR PUBLICATIONS

  • Negative Capacitance Field Effect Transistor with Modified Gate Stack and Drain-sided cavity for Label-free Biosensing
    H Kansal, AS Medury
    Semiconductor Science and Technology , 2024
    2024
    Citations: 3
  • Algorithm for Calibrating Effective Mass Parameters to consider Quantum Confinement Effects in Ultra-Thin-Body Devices for Various Temperatures
    NV Mishra, H Kansal, Y Dhote, R Solanki, AS Medury
    Journal of Electronic Materials, 1-9 , 2023
    2023
  • Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance
    H Kansal, AS Medury
    Microelectronics Journal 140, 105917 , 2023
    2023
    Citations: 1
  • Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices
    NV Mishra, H Kansal, R Solanki, AS Medury
    Journal of Physics D: Applied Physics 56 (41), 415102 , 2023
    2023
    Citations: 3
  • Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog …
    M Pratap, H Kansal, AS Medury
    Microelectronics Journal 136, 105777 , 2023
    2023
    Citations: 6
  • The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET
    H Kansal, AS Medury
    Silicon 15 (4), 1961-1966 , 2023
    2023
  • Temperature dependent band gap correction model using tight-binding approach for UTB device simulations
    NV Mishra, R Solanki, H Kansal, AS Medury
    IEEE Transactions on Nanotechnology 22, 8-13 , 2022
    2022
    Citations: 13
  • Confinement Effect and Conduction Band Offset in DG-SOI MOSFETs: A Simulation Study
    H Kansal, NV Mishra, AS Medury
    2022 International Semiconductor Conference (CAS), 281-284 , 2022
    2022
  • FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs
    H Kansal, AS Medury
    Microelectronics Journal 128, 105571 , 2022
    2022
    Citations: 1
  • Improved analog performance of FDSOI based NCFET with a ferroelectric–paraelectric–dielectric gate stack
    H Kansal, AS Medury
    Semiconductor Science and Technology 37 (10), 105007 , 2022
    2022
    Citations: 2
  • Negative capacitance partially junction-less FET for hysteresis-free and improved analog performance
    H Kansal, AS Medury
    Japanese Journal of Applied Physics 61 (8), 085003 , 2022
    2022
  • Comparison of Different Approaches used for Estimation of Electrostatics in UTB devices
    NV Mishra, H Kansal, R Solanki, AS Medury
    2022 IEEE 22nd International Conference on Nanotechnology (NANO), 347-350 , 2022
    2022
    Citations: 2
  • Hysteresis-free Behavior and Improved Performance of Negative Capacitance Optimized Bulk MOSFET
    H Kansal, AS Medury
    2022 IEEE Silicon Nanoelectronics Workshop (SNW), 1-2 , 2022
    2022
    Citations: 1
  • Analysis of Conduction Band Offset Variation on the Electrostatics of UTB Devices through the Modified Effective Mass Approximation (mEMA)
    H Kansal, N Vilochan Mishra, R Solanki, AS Medury
    TechRxiv , 2022
    2022
  • TCAD based modeling of sub-surface leakage in short channel bulk MOSFETs
    H Kansal, AS Medury
    2021 Joint International EUROSOI Workshop and International Conference on … , 2021
    2021
    Citations: 2
  • Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs
    H Kansal, AS Medury
    AIP advances 11 (2) , 2021
    2021
    Citations: 7
  • Towards novel channel doping profiles in short channel bulk mosfets for off-state current reduction and superior channel electrostatics
    H Kansal, AS Medury
    2020 IEEE Silicon Nanoelectronics Workshop (SNW), 105-106 , 2020
    2020
    Citations: 1
  • Quantum confinement effects and electrostatics of planar nano-scale symmetric double-gate SOI MOSFETs
    AS Medury, H Kansal
    2019 IEEE International Conference on Electron Devices and Solid-State … , 2019
    2019
    Citations: 8
  • Short-Channel Effects and Sub-Surface Behavior in Bulk MOSFETs and Nanoscale DG-SOI-MOSFETs: A TCAD Investigation
    H Kansal, AS Medury
    2019 Silicon Nanoelectronics Workshop (SNW), 1-2 , 2019
    2019
    Citations: 7

MOST CITED SCHOLAR PUBLICATIONS

  • Temperature dependent band gap correction model using tight-binding approach for UTB device simulations
    NV Mishra, R Solanki, H Kansal, AS Medury
    IEEE Transactions on Nanotechnology 22, 8-13 , 2022
    2022
    Citations: 13
  • Quantum confinement effects and electrostatics of planar nano-scale symmetric double-gate SOI MOSFETs
    AS Medury, H Kansal
    2019 IEEE International Conference on Electron Devices and Solid-State … , 2019
    2019
    Citations: 8
  • Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs
    H Kansal, AS Medury
    AIP advances 11 (2) , 2021
    2021
    Citations: 7
  • Short-Channel Effects and Sub-Surface Behavior in Bulk MOSFETs and Nanoscale DG-SOI-MOSFETs: A TCAD Investigation
    H Kansal, AS Medury
    2019 Silicon Nanoelectronics Workshop (SNW), 1-2 , 2019
    2019
    Citations: 7
  • Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog …
    M Pratap, H Kansal, AS Medury
    Microelectronics Journal 136, 105777 , 2023
    2023
    Citations: 6
  • Negative Capacitance Field Effect Transistor with Modified Gate Stack and Drain-sided cavity for Label-free Biosensing
    H Kansal, AS Medury
    Semiconductor Science and Technology , 2024
    2024
    Citations: 3
  • Band-structure based electrostatics model for ultra-thin-body double-gate silicon-on-insulator MOS devices
    NV Mishra, H Kansal, R Solanki, AS Medury
    Journal of Physics D: Applied Physics 56 (41), 415102 , 2023
    2023
    Citations: 3
  • Improved analog performance of FDSOI based NCFET with a ferroelectric–paraelectric–dielectric gate stack
    H Kansal, AS Medury
    Semiconductor Science and Technology 37 (10), 105007 , 2022
    2022
    Citations: 2
  • Comparison of Different Approaches used for Estimation of Electrostatics in UTB devices
    NV Mishra, H Kansal, R Solanki, AS Medury
    2022 IEEE 22nd International Conference on Nanotechnology (NANO), 347-350 , 2022
    2022
    Citations: 2
  • TCAD based modeling of sub-surface leakage in short channel bulk MOSFETs
    H Kansal, AS Medury
    2021 Joint International EUROSOI Workshop and International Conference on … , 2021
    2021
    Citations: 2
  • Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance
    H Kansal, AS Medury
    Microelectronics Journal 140, 105917 , 2023
    2023
    Citations: 1
  • FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs
    H Kansal, AS Medury
    Microelectronics Journal 128, 105571 , 2022
    2022
    Citations: 1
  • Hysteresis-free Behavior and Improved Performance of Negative Capacitance Optimized Bulk MOSFET
    H Kansal, AS Medury
    2022 IEEE Silicon Nanoelectronics Workshop (SNW), 1-2 , 2022
    2022
    Citations: 1
  • Towards novel channel doping profiles in short channel bulk mosfets for off-state current reduction and superior channel electrostatics
    H Kansal, AS Medury
    2020 IEEE Silicon Nanoelectronics Workshop (SNW), 105-106 , 2020
    2020
    Citations: 1
  • Algorithm for Calibrating Effective Mass Parameters to consider Quantum Confinement Effects in Ultra-Thin-Body Devices for Various Temperatures
    NV Mishra, H Kansal, Y Dhote, R Solanki, AS Medury
    Journal of Electronic Materials, 1-9 , 2023
    2023
  • The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET
    H Kansal, AS Medury
    Silicon 15 (4), 1961-1966 , 2023
    2023
  • Confinement Effect and Conduction Band Offset in DG-SOI MOSFETs: A Simulation Study
    H Kansal, NV Mishra, AS Medury
    2022 International Semiconductor Conference (CAS), 281-284 , 2022
    2022
  • Negative capacitance partially junction-less FET for hysteresis-free and improved analog performance
    H Kansal, AS Medury
    Japanese Journal of Applied Physics 61 (8), 085003 , 2022
    2022
  • Analysis of Conduction Band Offset Variation on the Electrostatics of UTB Devices through the Modified Effective Mass Approximation (mEMA)
    H Kansal, N Vilochan Mishra, R Solanki, AS Medury
    TechRxiv , 2022
    2022