Harshit Kansal
@harshitk@iiserb.ac.in
Research Associate
indian institute of science education and research bhopal
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Electrical and Electronic Engineering, Engineering
Scopus Publications
Scholar Citations
Scholar h-index
Scopus Publications
Nalin Vilochan Mishra, Harshit Kansal, Yogesh Dhote, Ravi Solanki, and Aditya Sankar Medury
Springer Science and Business Media LLC
Nalin Vilochan Mishra, Harshit Kansal, Ravi Solanki, and Aditya Sankar Medury
IOP Publishing
Abstract The effect of quantum confinement has become significant in terms of its impact on the scalability and electrostatics of ultra-thin-body double-gate MOSFETs. In this paper, we present a simplified model to account for the effect of quantum confinement, considering the contribution of the ground-state and the first excited state of the conduction band, on the electron carrier concentration, which when incorporated into the 1-D Poisson’s equation, enables the determination of the electrostatic potential. We establish the accuracy of the proposed model, over a wide range of process and electrical parameters, through aggressively benchmarking the electrostatics parameters obtained from the proposed model with results from the sp 3 d 5 s ∗ tight-binding method (TBM), over a wide range of device temperatures. Furthermore, a simplified model for the integrated channel charge density is shown in the form of a diffusion layer charge where the thickness and potential of this layer, while being gate voltage dependent, enables the channel charge density obtained from the model to agree well with results from TBM. Through this physics based and accurate model for the integrated charge, a simplified understanding of the gate capacitance is shown as a series combination of the diffusion layer capacitance, strong-inversion capacitance and oxide capacitance, which includes the effects of structural confinement as well as charge confinement at low and high gate voltages, respectively.
Harshit Kansal and Aditya Sankar Medury
Elsevier BV
Manas Pratap, Harshit Kansal, and Aditya Sankar Medury
Elsevier BV
Harshit Kansal and Aditya Sankar Medury
Springer Science and Business Media LLC
Nalin Vilochan Mishra, Ravi Solanki, Harshit Kansal, and Aditya Sankar Medury
Institute of Electrical and Electronics Engineers (IEEE)
In order to accurately determine the electrostatics of Ultra-Thin-Body (UTB) devices, the semi-empirical tight-binding (TB) approach is widely used for calculating the channel thickness dependent band structure of any material at those temperatures where TB parameters are available (generally defined at 0 K and 300 K). In this work, we analyze the variation of band structure for Si, Ge, and GaAs over different channel thicknesses at 0 K and 300 K, and show that the band curvature at the band minima remains unchanged with temperature, while the band gap changes significantly and affects the channel electrostatics. Based on this finding, we propose an approach to simulate the electrostatics of UTB devices, at any temperature between 0 K and 300 K, using the band structure obtained at 0 K, along with a suitable channel thickness and temperature-dependent band gap correction. From the results obtained for the channel charge density, we show good agreement with band structure based simulation results, at 300 K, over a wide range of channel thicknesses, for Si, Ge, and GaAs, while also showing good agreement with TCAD simulation results, at a typical intermediate temperature of 150 K, thus highlighting the accuracy, simplicity and wide applicability of the proposed approach.
Harshit Kansal and Aditya Sankar Medury
Elsevier BV
Harshit Kansal and Aditya Sankar Medury
IOP Publishing
Abstract With the superior analog/RF performance of planar device architectures such as fully depleted silicon-on-insulator (FDSOI) MOSFETs, it becomes important to investigate the impact of a ferroelectric material in the gate stack, resulting in negative capacitance (NC) behavior, on the device performance. In this work, through calibrating the FDSOI MOSFET (as the baseline device architecture) with experimental data, we compare the impact of ferroelectric–dielectric (FE–DE) and ferroelectric–paraelectric–dielectric (FE–PE–DE) gate stacks on the electrostatics of an NCFET device for a practically realisable metal–ferroelectric–insulator–semiconductor (MFIS) structure. A suitable thickness of the ferroelectric (FE) layer in the FE–DE stack and the maximum drain–source voltage ( V d s ) that can be applied (determining the power supply voltage), are identified so as to ensure that constraints such as no negative differential resistance (NDR) effects, threshold voltage ( V t h ), sub-threshold slope (SS) invariability with drain voltage variations and hysteresis-free behavior in transfer characteristics ( I d – V g s ) are all satisfied. From the thickness of the FE layer in the FE–DE stack, the thickness of the FE layer in the FE–PE–DE stack (PE layer thickness is fixed at 1 nm) is determined where with a thicker FE layer, we obtain similar capacitance from the FE–PE–DE gate stack to that obtained from the FE–DE stack, while meeting all the constraints applied to the FE–DE stack based NCFET, enabling determination of the power supply voltage. Through showing good SSs with reduced output conductance ( g d s ), resulting in improved dc gain ( g m g d s ) and improved linearity parameters ( g m 2 and g m 3 ) along with scaling of power supply, an FE–PE–DE stack shows better analog performance, with lower power consumption, compared to an FE–DE stack, for an FDSOI NCFET, at 14 nm gate length.
Harshit Kansal and A. S. Medury
IOP Publishing
Abstract Given the advantage of high transconductance (g m) at low gate voltages (V gs), seen in junction-less (JL) transistors, it becomes important to incorporate these advantages in conventional bulk MOSFETs which have thus far been used extensively for analog circuit applications. In this work, we propose a partially JL channel in a bulk MOSFET device, which when investigated for a metal-ferroelectric-insulator-semiconductor (MFIS) with negative capacitance field-effect transistor (NCFET) shows superior analog device performance, with improved scalability. Through technology computer aided design (TCAD)-based transient simulations, we identify an optimum and almost constant ferroelectric layer thickness for different gate lengths, which enables hysteresis-free behavior, along with reasonably steep sub-threshold slopes (SS), that meets international roadmap for devices and systems specifications. For this device, we then determine the maximum drain voltage, V ds, which ensures no drain-induced barrier raise effects, based on which improved transconductance generation efficiency (g m/I d), with minimal gate induced drain leakage is shown.
Nalin Vilochan Mishra, Harshit Kansal, Ravi Solanki, and Aditya Sankar Medury
IEEE
With the scaling of SOI channel and oxide thicknesses in Ultra-thin Body (UTB) devices, Quantum Confinement Effects (QCEs) becomes significant and need to be considered for accurate estimation of electrostatics parameters such as electron density inside the channel. In this work, we propose to use a $sp^{3}d^{5}s^{\\ast}$ Tight-Binding (TB) scheme by suitably selecting the significant k-points around the band minima, which makes this approach computationally efficient while being accurate to account for Quantum Confinement Effects. Thus through comparison of electrostatics obtained from other approaches, such as Effective Mass Approximation (EMA) used by SCHRED and Density Gradient Approach (DGM) used in TCAD, we show the importance of using the TB based approach as it is shown to be far more accurate in considering Quantum confinement effects compared to other existing approaches.
Harshit Kansal, Nalin Vilochan Mishra, and Aditya Sankar Medury
IEEE
Besides Quantum Confinement Effects (QCEs) seen in Ultra-Thin (UT) channel Double-Gate Silicon on Insulator (DG-SOI) MOS devices, the Band-offset variations between the oxide and the UT channel also impact device electrostatics, which is not adequately considered by the existing TCAD Models. Effective Mass Approximation (EMA) is one of the widely used approach which takes both QCEs and Conduction Band offset (CBO) variations into account. In this work, we ensure the accuracy of the EMA approach through benchmarking the results with the Tight-Binding Method (TBM), for an infinite potential well (equivalent to considering high CBO) case. Having corrected effective mass while also inserting suitable energy correction parameters, the accuracy of the EMA approach is now ensured. In this work, we show that by reducing the band-gap of the oxide material, the integrated charge density obtained using the Direct Tunneling (DT) model in TCAD can now accurately emulate the results obtained from the benchmarked Effective Mass Approximation (EMA) approach.
Harshit Kansal and Aditya Sankar Medury
IEEE
Despite the use of High-k gate stacks, poor channel electrostatics at short channel lengths has limited the applicability of conventional Bulk MOSFETs. In this paper, we firstly present the design of an optimized N-channel Partially Junction-less Bulk MOSFET with a view to suppressing various leakage mechanisms, while also taking channel quantization effects into account. Through detailed process simulations, the process steps required to achieve the identical transfer characteristics are determined, thus providing a more practical appraisal of the feasibility of the device, where the threshold voltage (Vth), sub-threshold slope (SS) and ION/IoFF ratio are nearly identical for both the devices. Furthermore, through the inclusion of ferroelectric layer of suitable thickness over the existing gate stack, we show a significant improvement in the device performance, while ensuring hysteresis-free behavior in transfer characteristics.
Harshit Kansal and Aditya Sankar Medury
IEEE
Aggressive scaling of the channel length of Bulk MOSFETs manifests in higher sub-surface leakage current, which becomes an increasingly significant component of the OFF-State leakage current. By firstly identifying the sub-surface leakage region as one that manifests in a region away from the electrostatic control of the gate, but, within the source/drain junction depth, while being impacted by the drain voltage, we model the sub-surface leakage current using a non-charge-sheet based approach, which is further simplified as a physics-based semi-analytical model similar to the Shockley equation of an ideal ‘forward-biased’ p-n junction diode. In addition to validating the proposed model, we also show the impact of various structural and electrical parameters, thus demonstrating that the model provides key insights on device behaviour.
Harshit Kansal and Aditya Sankar Medury
AIP Publishing
Quantum confinement effects tend to diminish gate control over the channel, further degrading the channel electrostatics of short channel Double-Gate (DG) Silicon-on-Insulator (SOI) MOSFETs. In this work, we first design an n-channel Junction-less (JL) DG MOSFET with a channel length (Lg) of 10 nm, where the source/drain doping, determined through Technology Computer-Aided Design (TCAD) simulations, enables better gate control for different channel thicknesses (tch) and oxide thicknesses (tox). The source/drain doping, thus determined, enables JL DG MOSFETs to overcome quantum confinement effects while also achieving key ITRS (International Technology Roadmap for Semiconductors) targets in terms of sub-threshold slope (S) and threshold voltage (Vth). We then introduce a heavily doped symmetric p-type silicon layer at the interface of the channel region with the top/bottom oxide such that the thickness and doping of the p-type layer enable tuning of the threshold voltage. In this partially JL DG MOSFET, by replacing the n-type doped silicon with n-type silicon–germanium (Si0.7Ge0.3) of lower doping, determined through TCAD simulations, we continue to demonstrate excellent channel electrostatics (ITRS targets) at short channel lengths (Lg = 10 nm) over a wide range of channel and oxide thicknesses while also showing enhanced strong inversion channel currents.
Harshit Kansal and Aditya Sankar Medury
IEEE
For short channel MOS Transistors, leakage current flowing underneath the Si/SiO2 interface (sub-surface leakage) both within the source-drain junction depth, as well as the current flowing through the bulk, are found to significantly contribute to the OFFState current (IOFF). Through TCAD Simulations, we firstly identify the region most susceptible to sub-surface leakage and then compare channel doping profiles such as the Uniformly doped (UD) and Super-Steep Retrograde (SSR), with a view to reducing IOFF. This comparison enables us to propose a novel doping profile in the channel, demonstrating a higher ON-State current (ION) compared to the SSR channel doping, while showing a comparable OFF-State current, both for Vds = 0.05 V and Vds = 1 V.
Harshit Kansal and Aditya Sankar Medury
IEEE
Using TCAD simulations, we have identified the existence of a sub-surface conducting region, below the Si/SiO2 interface, with significant electron concentration, in short channel bulk MOSFETs (p-type silicon substrate), at high accumulation bias. This is symptomatic of weakening gate control. The electron concentration in this sub-surface region is shown to be dependent on oxide thickness, channel length and source-drain junction depth. In the case of short channel nanoscale Double Gate SOI (DGSOI) MOSFETs, studied for different SOI channel thicknesses, despite quantum confinement effects, the electron concentration is found to be considerably reduced at lower SOI channel thicknesses, compared to Bulk MOSFETs.
Aditya Sankar Medury and Harshit Kansal
IEEE
The effects of quantum confinement on the charge distribution in planar Double-Gate (DG) SOI (Silicon-on-Insulator) MOSFETs were examined, for sub-10 nm SOI film thicknesses $({\\mathrm {t_{si}}}\\ \\leq\\ 10\\ nm)$, by modeling the potential experienced by the charge carriers as that of an an-harmonic oscillator potential, consistent with the inherent structural symmetry of nanoscale symmetric DGSOI MOSFETs. By solving the 1-D Poisson’s equation using this potential, the results obtained were validated through comparisons with TCAD simulations. The present model satisfactorily predicted the electron density and channel charge density for a wide range of SOI channel thicknesses and gate voltages.