Renewable Energy, Sustainability and the Environment, Electrical and Electronic Engineering
44
Scopus Publications
Scopus Publications
A simulation study of 7 nm Si-based Multiple Gate Material Nanosheet Field Effect Transistors Shankhamitra Sunani, Satya Sopan Mahato, Narayan Sahoo, Asisa Kumar Panigrahy, Raghunandan Swain Semiconductors, 2025 We propose a 7 nm high-k gate stack triple material gate (TMG) nanosheet field effect transistor (NSFET) and compare its DC characteristics with a single material gate (SMG) NSFET. The transfer characteristics ( $${{I}_{{\text{D}}}}$$ – $${{V}_{{{\text{GS}}}}}$$ ), output characteristics ( $${{I}_{{\text{D}}}}$$ – $${{V}_{{{\text{DS}}}}}$$ ), drain-induced barrier lowering ( $${\text{DIBL}}$$ ), subthreshold swing ( $$SS$$ ), ON current (ION) to OFF current (IOFF) ratio (ION/IOFF) are estimated, compared and analyzed. ION/IOFF of 108 and 104, DIBL of 22.22 and 44.44 mV/V, and $$SS$$ of 80 mV/dec and 90 mV/dec are obtained for TMG and SMG NSFET respectively. We also analyzed RF performance characteristics of SMG and TMG NSFETs like transconductance ( $${{g}_{m}}$$ ), output conductance ( $${{g}_{d}}$$ ), transconductance generation factor ( $${\text{TGF}}$$ ), and early voltage (VEA). Additionally, we have examined SMG and TMG NSFET Parasitic capacitance ( $${{C}_{{gg}}}$$ ), cut-off frequency ( $${{f}_{{\text{T}}}}$$ ), dynamic power, and average power. These values suggest that the TMG NSFET device has improved DIBL, SS, and ION/IOFF switching, less leakage current, improved capacitance and frequency characteristics compared to SMG NSFET, suitable for improved Power, Performance and Area (PPA).
Design and Performance Analysis of Single Material and Triple Material Cylindrical Gate All Around Gate Stack Silicon Nanowire FET at 7 nm Technology node Shankhamitra Sunani, Satya Sopan Mahato, Raghunandan Swain Indiscon 2025 IEEE 6th India Council International Subsections Conference Proceedings, 2025 In this work, we examine single material (SM) and triple material (TM) cylindrical gate all around (CGAA) silicon nanowire field effect transistor (Si-NWFET), and simulation findings are presented using Cogenda 3D TCAD tool. The analysis encompasses an evaluation of essential electrical characteristics such as drain-induced barrier lowering (DIBL), subthreshold swing (SS), on current ($I_{\text {ON }}$), off current ($I_{\text {OFF }}$), on-off current ratio $\left(\frac{I_{O N}}{I_{O F F}}\right)$, transconductance $\left(g_{m}\right)$, transconductance generation factor (TGF), output conductance $\left(g_{d}\right)$, and early voltage ($V_{E A}$), which are assessed for both the SM and TM CGAA NWFET. The device shows a DIBL of $88 \mathrm{mV} / \mathrm{V}$ and $44 \mathrm{mV} / \mathrm{V}$, with SS of $120 \mathrm{mV} /$ dec and $100 \mathrm{mV} / \mathrm{dec}$, while $\boldsymbol{I}_{\boldsymbol{O} \boldsymbol{N}} / \boldsymbol{I}_{\boldsymbol{O F F}}$ Values of $10^{\mathbf{5}}$ and $10^{\mathbf{6}}$ are obtained for SM CGAA NWFET and TM CGAA NWFET, respectively. Further, the device demonstrates RF performance metrics with $g_{m}$ of $56.67 \mu \mathrm{~S}$ and $38.33 \mu \mathrm{~S}$ at $\mathrm{V}_{\mathrm{GS}}=0.9 \mathrm{~V}$ and 1 V, TGF of $18.85 \mathrm{~V}^{-1}$ and $18.30 \mathrm{~V}^{-1}$ for SM and TM CGAA NWFET. Additionally, a $37 \%$ reduction of $g_{d}$ and a $41 \%$ enhancement in $V_{E A}$ are noted in TM CGAA NWFET in comparison to SM CGAA NWFET. Therefore, the well-designed TM CGAA NWFET emerges as a promising option for low power consumption and improved linearity in future technologies.
Hot carrier degradation in nanowire (NW) FinFETs T. K. Maiti, M. K. Bera, S. S. Mahato, P. Chakraborty, C. Mahata, M. Sengupta, A. Chakraborty, C. K. Maiti Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits IPFA, 2008
Stress-induced degradation in strain-engineered nMOSFETs T. K. Maiti, S. S. Mahato, M. K. Bera, M. Sengupta, P. Chakraborty, C. Mahata, A. Chakraborty, C. K. Maiti Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits IPFA, 2008
DIBL in short-channel strained-Si n-MOSFET S. S. Mahato, P. Chakraborty, T. K. Maiti, M. K. Bera, C. Mahata, M. Sengupta, A. Chakraborty, S. K. Sarkar, C. K. Maiti Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits IPFA, 2008
Technology CAD of non-volatile SONOS memory devices P. Chakraborty, S. S. Mahato, T. K. Maiti, S. Saha, C. K. Maiti Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices Iwpsd, 2007
Radiation effects on strain-engineered p-MOSFETs T. K. Maiti, S .S. Mahato, P. Chakraborty, S. K. Sarkar, C. K. Maiti Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices Iwpsd, 2007
Low temperature behavior of strained-Si n-MOSFETs S. S. Mahato, T. K. Maiti, P. Chakraborty, D. Mitra, B. Senapati, A. Chakravorty, S. K. Sarkar, C. K. Maiti Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices Iwpsd, 2007
