Padma Challa received her M.Tech degree in VLSI System Design from JNTUA Ananthapuramu in 2013, and Ph.D in the area of VLSI and Signal Processing from Jawaharlal Nehru Technological University Ananthapuramu (JNTUA) in 2023, and is now currently working as Associate Professor in ECE department at Sri Venkateswara College of Engineering, Tirupati. Her area of interests includes Low Power VLSI Architecures, Signal Processing and IOT. She can be contacted at email: padmasekhar85@
Engineering, Electrical and Electronic Engineering, Computer Science Applications, Agricultural and Biological Sciences
15
Scopus Publications
62
Scholar Citations
4
Scholar h-index
2
Scholar i10-index
Scopus Publications
Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits Journal of VLSI Circuits and Systems, 2025 The main areas of research in VLSI system design include area, high speed, and powerefficient data route logic systems.The amount of time needed to send a carry through the adder limits the pace at which addition can occur in digital adders.One of the quickest adders, the Carry Select Adder (CSLA), is utilized by various data processing processors to carry out quick arithmetic operations.It is evident from the CSLA's structure that there is room to cut back on both the area and the delay.This work employs a straightforward and effective gate-level adjustment (in a regular structure) that significantly lowers the CSLA's area and delay.In light of this adjustment Square-Root Carry Select Adder (SQRT CSLA) designs with bit lengths of 8, 16, 32, and 64.When compared to the standard SQRT CSLA, the suggested design significantly reduces both area and latency.Xilinx ISE tool is used for Simulation and synthesis.The performance of the recommended designs in terms of delay is estimated in this study using the standard designs.The study of the findings indicates that the suggested CSLA structure outperforms the standard SQRT CSLA.
An Efficient 32-Bit Carry Look Ahead Adder using PFAL for Low Power Circuits Shaik Hibza, C. Padma 2025 Global Conference on Information Technology and Communication Networks Gitcon 2025, 2025 Adders are digital circuits used in VLSI (Very Large Scale Integration) architecture that carry out arithmetic operations, particularly addition, on binary values. They are employed in a wide range of devices, such as memory systems, digital signal processors, and microprocessors. Logic gates that accept two binary values as inputs and output a binary sum make up an adder. These days, designing low power VLSI circuits heavily relies on low power circuits. Adiabatic circuits explain reversible logic, or the reuse of the same, which results in power savings. Using the traditional approach, CMOS circuits are utilized to lower circuit power dissipation. A number of adiabatic techniques were developed to address the shortcomings of CMOS circuits. These techniques use charging and discharging to further reduce power dissipation. Efficient Charge Recovery Logic (ECRL) and Positive Feedback Adiabatic logic (PFAL) are the methods employed. Arithmetic operations, such as adder and multiplier, require full adders. In this paper, we will examine the designs of adiabatic logic and develop a new complete adder employing PFAL logic, followed by simulations. Consequently, the circuits' effectiveness is displayed and contrasted utilizing the nano meter technologies. By lowering the amount of circuit delay, the Carry Look a Ahead Adder— also referred to as FAST ADDER—also plays a significant role. Since delay is a significant factor in LOW POWER VLSI CIRCUITS, the power dissipation in the full adder is decreased by employing the adiabatic technique. When comparing ECRL and PFAL, the power dissipation is decreased in both, but PFAL is somewhat more lowered. Tanner EDA Tool simulates every circuit utilizing 22 nm Technology.
Implementation of I2C Protocol with Adaptive Baud Rate for N Number of Bits Using VERILOG S Aparna, C. Padma Proceedings 2025 7th International Conference on Control Systems Mathematical Modeling Automation and Energy Efficiency Summa 2025, 2025 For low-speed peripherals in embedded systems, the Inter-Integrated Circuit (I2C) protocol is a popular serial communication standard. In order to accommodate variable communication speeds depending on system requirements, this paper outlines the construction of an I2C protocol with an adaptable baud rate. The design is appropriate for FPGA-based applications because it is built using Verilog HDL. N-bit data width is supported by the suggested system, enabling capability for a range of applications. To maximize efficiency and minimize battery usage, the adaptive baud rate system constantly modifies the transmission speed. Key elements of the I2C master-slave communication framework include clock stretching, data transmission/reception, start/stop condition detection, and acknowledgment processing. Results from simulation and synthesis show how well the architecture works to provide dependable, fast communication while preserving compatibility. A result from simulation and synthesis is showing how well the design works to achieve dependable, fast communication while being compatible with common I2C devices. Applications need low power consumption and adjustable data transfer speed, effective serial transmission, including FPGA-based embedded systems, real-time data gathering, and sensor interface would benefit greatly from the suggested approach.
DESIGN AND ANALYSIS OF PARTITION TECHNIQUE BASED DADDAMULTIPLIER ARCHITECTURE D. Kalaiyarasi, T. Suguna, C. Padma, C. Nalini, M. Sundar, G. Nagarajan Arpn Journal of Engineering and Applied Sciences, 2025 This paper combines two design strategies to speed up column compression multiplication using the Dadda algorithm: decomposing partial products into two sections so that they can be compressed individually in parallel columns and added more quickly using a ripple carry adder and a Binary to Excess-1 converter. This paper also proposes multiplexer based full adder and a half adder designs to optimize power dissipation and propagation delay. The proposed Dadda multiplier of size 8,16,32 and 64 is designed by employing proposed adder designs and is simulated and synthesized using Altera Quartus II with EP2S15F484C3 device for 90nm technology of supply voltage of 1.2V and observed the performance parameters such as delay, power, Maximum Usable Frequency (MUF), Power Delay Product (PDP) and area respectively. It is observed that the proposed partitioned Dadda multiplier in this work,on an average, was able to minimize ALUTs utilization by 73.16%, delay by 51.57%, power by 47.38%, PDP by 73.89% and MUF in an average is increased by 51.57% when compared to existing works. It is concluded that the suggested multiplier can be employed in applications where power and propagation delay are of major concerns since the proposed multiplier design has substantially optimized for all the performance parameters than the conventional Dadda multiplier.
PERFORMANCE OPTIMIZED GROUP DECOMPOSITION DADDA MULTIPLIER FOR DSP APPLICATIONS Arpn Journal of Engineering and Applied Sciences, 2025 This study introduces an extremely fast grouping and decomposition multiplier, providing a novel method of binary multiplication. The suggested multiplier combines the Wallace tree and Dadda multiplier with an innovative grouping and decomposition method such that a total number of partial products and critical path delay are minimized. The full adder used in the proposed multiplier structure is designed by using the GDI technique. The proposed multiplier is implemented using a 45 nm CMOS technology and evaluated against state-of-the-art binary multipliers in terms of speed, power consumption, and area. It is observed from the results that the suggested multiplier has improved performance when compared with existing multipliers. It is concluded that the PDP of the proposed 8-bit Group Decomposition Multiplier (PGDM) with the mentioned multipliers is reduced by 68.11%, 65.63% and 30.72% when compared with the 8-bit Wallace tree, Dadda multiplier and Group Decomposition (GD) multiplier respectively and hence concluded that the proposed multiplier design can be employed in DSP applications for high-speed digital signal processing applications including audio and video processing.
Hardware Efficient Implementation of Image Enhancement Algorithms Using Xilinx System Generator Neelima. K, P. Rajyalakshmi, Attar Farooq Hussain, T. Suguna, Venkata Syamala Raju Talari, C. Padma International Conference on Intelligent Communication Networks and Computational Techniques Icicnct 2025, 2025 Image enhancement is a vital component in image processing pipelines. With increasing demand for real-time and high-quality visual data, both traditional and modern AI-driven methods play a role in producing clearer, more usable images. Continued advancements in adaptive and deep learning techniques offer promising enhancements across diverse domains. The optimization at various hardware levels of abstraction varies with complexity and time. The design of image and video processing algorithms induces high time and space complexity with hardware implementation. To reduce design time and to suit hardware models, MATLAB Simulink and Xilinx System generator can utilize Xilinx block sets for FPGA implementation. To improve visual appearance and analytical quality of Images, this paper presents a few image enhancement techniques like image negative, contrast stretching, brightness control, etc by using Xilinx block sets. The algorithms utilize preprocessing and postprocessing steps to generate appropriate output as per the algorithm. The images are processed for parameters like mean, variance, standard deviation, kurtosis, etc. The results prove that the developed models are quite simple and easy to utilize. Also, the spatial enhancement was improved by 12 %, PSNR by 4.2 %, LUTs by 3 %, DSP Slices by 4.44 % and Latency by 6.67 % when compared with existing algorithms.
Adept Domino Logic for Modified Schmitt Trigger Circuits Neelima K, K. Maheswari, Syed Sadiq Vali, CH. Pallavi, C. Padma, Jaffar Ali Shaik International Conference on Computing Intelligence and Application Ciacon 2025, 2025 Schmitt trigger circuit generates square wave to serve as clock signals. The CMOS based designs have gained enormous popularity due to suppressed spikes in the output signal with good packing density. As the technology started to shrink, low power design became a priority. This paper focuses on design of Schmitt trigger circuits with advanced domino logic with integration of low power techniques like clocked delayed dual keeper, foot driven stacked transistor, ground PMOS keeper, high speed domain, leakage control replica keeper, proficient clock delayed dual keeper, etc as schematics in DSCH and the respective layouts in Microwind Tool for technologies like 90nm, 65nm, 45nm and 32nm. The area and power dissipation are measured from HSPICE Tool. From results, it is found that even though the area occupied by proficient Schmitt trigger circuits is slightly more by 1.07% to 2.32%, the power dissipation is less by 7.23%. Also, the leakage current based Schmitt trigger circuits dissipate less power due to design with lesser number of transistors.
Post-Pandemic Economy - Shocks, Risks and Suggestive Measures K Neelima, C.H. Kavya, C. Padma, T. Suguna Economic Uncertainty in the Post Pandemic Era Policy Responses and the Way Forward, 2024 The novel COVID-19 had an unprecedented impact on society around the globe. The two major effects being loss of human life and the other being economic crisis at a large scale. The demand–supply shocks were adversely affected as the consumers reduced the demand from 90% to 70%, while the supply was reduced to 16% due to unemployment issues. The supply shock effects vary across different industries. The least affected industries are power generation and distribution, legal services, scientific research labs, etc. But the most affected industries include transport, tourism, hospitality, mining, manufacturing, and some human contactless service sectors. The dominating demand shock was seen in industries related to entertainment, restaurants, and hotel experiences which experienced huge demand and supply shocks due to the majority of the service sector being used to work from home. Post-pandemic scenarios for employees varied from work from home to onsite. The COVID-19 pandemic effects on income include workplace absenteeism and premature deaths paved the way to reduced productivity due to disruptions in the global supply chain and the closure of industries/factories. Hence pandemic initiated fiscal in the short-term to economic impact in long-term across the world resulting in declined tax revenues from lower middle-income countries due to shortage of labor caused by illness, fear-induced behavior, rise in mortality, etc. Further restricted trade and travel slowed down the economic growth. Many countries associated with International Air Transport witnessed severe loss in revenue solely of $314 billion from passenger carriage. The leading US and European stock market indices have fallen by a quarter value, with >65% decline in prices of oil prices. Even daily stock market and price movements have turned up to be negative relationship for the world economy due to present and future demands of oil price fluctuations. As many migrants had to move back to their home town, caused a shock to the labor markets with imbalances in occupations. Amidst these economic dangers still prevailing, there exist ways to improve the global supply chains by enhancing domestic production easing transportation jams, through on-shoring and near-shoring, managing labor shortages, prioritizing public health, mitigating geopolitical tensions, etc. This chapter details the economy-related shocks, risks involved and suggestive measures in post-pandemic situations.
Efficient Approximate Adders for Image Processing Applications C. Padma, Suresh Babu Potladurty, C. Nalini, T. Suguna, CH. Pallavi 2024 International Conference on Advances in Computing Research on Science Engineering and Technology Acroset 2024, 2024 This effort sacrificed accuracy in order to design fast, energy-efficient adders. In order to minimize propagation delay and reduce power consumption, the proposed design truncates half of the adder area. Additionally, internal stage input-output pipelining to the parallel prefix adder can further optimize propagation delay to half of its original value. By significantly raising the approximation adder error, the MSP minimizes the parameters while utilizing the exact calculation and LUTs as resources. In comparison to the current LEADx and APEx, our proposed adder is now efficient in terms of parameters. Xilinx Vivado is used to synthesize the design, simulation, and efficacy of the suggested method. As a case study, the suggested approximation adders are applied in a video encoding application. For video encoding applications, LEADx provided superior quality when compared to other types of approximation adders. Thus, our suggested approximate adders can be useful in efficient FPGA designs of error-tolerant applications.
High Speed Single Precision 64-Tap FIR Filter Using Urdhva Tiryagbhyam Sutra Satyam, Neelima K, M. Sandhiya, C. Padma, Shaik Jaffar Ali, Kumar Raja Meruva 2024 IEEE Students Conference on Engineering and Systems Interdisciplinary Technologies for Sustainable Future Sces 2024, 2024 In high computing applications like signal and image processing, the computational demand for floating-point multiplication remains paramount. However, the intrinsic complexity of this operation translates into substantial time and power consumption. Addressing this challenge, this paper presents a novel and efficient methodology for IEEE 754 floating-point 64-tap FIR Filter, with a primary emphasis on minimizing both delays in time and area utilization. The Urdhva Tiryagbhyam sutra is used to reduce the delay in multiplication. This paper presents a process to devise filter coefficients and implementation of them for 64-tap 32-bit FIR filter design, which are modeled in Verilog HDL and implemented for XC7K70TFBV676-1 Kintex-7 FPGA board in Xilinx Vivado Tool. The obtained results prove that the proposed FIR filter design proves to be better than the existing FIR filter design as it reduces area by 51.11%, delay by 45.83% and power dissipation by 19.49%. Also the proposed FIR filter design proves to be better than the existing FIR filter design as it reduces Area Delay Product by 73.52% and Power Delay Product by 56.39%.
Implementation of high performance FFT architecture for DSP applications International Journal of Advanced Science and Technology, 2020
RECENT SCHOLAR PUBLICATIONS
Comparative Analysis of 32-bit Carry look ahead Adder using ECRL and PFAL Logic CP SHAIK HIBZA INTERNATIONAL JOURNAL OF CREATIVE RESEARCH THOUGHTS - IJCRT 13 (11), 232-242 , 2025 2025
Implementation of I2C Protocol with Adaptive Baud Rate for N Number of Bits Using VERILOG CP S Aparna 2025 7th International Conference on Control Systems, Mathematical Modeling … , 2025 2025
Hardware Efficient Implementation of Image Enhancement Algorithms Using Xilinx System Generator PC Neelima Koppala, P. Rajyalakshmi, Attar Farooq Hussain, Suguna Tangimi ... 2025 International Conference on Intelligent Communication Networks and … , 2025 2025
An Efficient 32-Bit Carry Look Ahead Adder using PFAL for Low Power Circuits. CP Shaik Hibza 2025 Global Conference on Information Technology and Communication Networks … , 2025 2025
Adept Domino Logic for Modified Schmitt Trigger Circuits K Neelima, K Maheswari, SS Vali, CH Pallavi, C Padma, JA Shaik 2025 International Conference on Computing, Intelligence, and Application … , 2025 2025
DESIGN AND ANALYSIS OF PARTITION TECHNIQUE BASED DADDAMULTIPLIER ARCHITECTURE D Kalaiyarasi, T Suguna, C Padma, C Nalini, MS Raj, G Nagarajan 2025
PERFORMANCE OPTIMIZED GROUP DECOMPOSITION DADDA MULTIPLIER FOR DSP APPLICATIONS PVKKVLK Suguna T. , Kalaiyarasi D. , C. Padma , R. Kiran Kumar 2025
Post-Pandemic Economy–Shocks, Risks and Suggestive Measures K Neelima, CH Kavya, C Padma, T Suguna Economic Uncertainty in the Post-Pandemic Era, 187-197 , 2024 2024 Citations: 1
Design of a 64-bit SQRT-CSLA with reduced area and high-speed applications in low power VLSI circuits CH Pallavi, C Padma, RK Kumar, T Suguna, C Nalini arXiv preprint arXiv:2410.15736 , 2024 2024 Citations: 1
Improved Domino Logic based Low Power CMOS Schmitt Trigger Circuit at Nano Scale Regime P Challa, C Nalini, S Tangimi, N Koppala Journal of Advanced Research in Applied Sciences and Engineering Technology … , 2024 2024
Efficient approximate adders for image processing applications C Padma, SB Potladurty, C Nalini, T Suguna, CH Pallavi 2024 International Conference on Advances in Computing Research on Science … , 2024 2024 Citations: 4
High Speed Single Precision 64-Tap FIR Filter Using Urdhva Tiryagbhyam Sutra K Neelima, M Sandhiya, C Padma, SJ Ali, KR Meruva 2024 IEEE Students Conference on Engineering and Systems (SCES), 1-5 , 2024 2024 Citations: 1
Post-Pandemic Biometric Challenges and Solutions: A Shocker to Supply Chain K Neelima, B Madhavi, C Padma, BK Pandey, G Gowwrii, SS Manaktala AI and Machine Learning Impacts in Intelligent Supply Chain, 196-208 , 2024 2024 Citations: 4
Hybrid Cryptography and Steganography-Based Security System for IoT Networks T Suguna, C Padma, MJ Rani, GP Priya International journal on recent innovation trends in computing and … , 2023 2023 Citations: 2
FIR filter design using urdhva triyagbhyam based on truncated wallace and dadda multiplier as basic multiplication unit K Neelima, C Padma, C Nalini, M Balaji 2023 IEEE 12th International Conference on Communication Systems and Network … , 2023 2023 Citations: 13
A Novel Approach for the Analysis on Classification of ILDs Using HRCT Images K Praveena, C Nalini, C Padma International Conference on Intelligent Healthcare and Computational Neural … , 2022 2022
Efficient cached 64 point FFT processor using floating point arithmetic for OFDM application C Padma, P Jagadamba, RR Patil Instrumentation, Mesure, Metrologie 21 (1), 21 , 2022 2022 Citations: 3
Design of FFT processor using low power Vedic multiplier for wireless communication C Padma, P Jagadamba, PR Reddy Computers & Electrical Engineering 92, 107178 , 2021 2021 Citations: 17
Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications C Padma Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12 (10 … , 2021 2021
Implementation of High Performance FFT Architecture for DSP Applications C.Padma, P.Jagadamba, P. Ramana Reddy International journal of Advanced Science and Technology (IJAST) 29 (No.3 … , 2020 2020 Citations: 3
MOST CITED SCHOLAR PUBLICATIONS
Design of FFT processor using low power Vedic multiplier for wireless communication C Padma, P Jagadamba, PR Reddy Computers & Electrical Engineering 92, 107178 , 2021 2021 Citations: 17
FIR filter design using urdhva triyagbhyam based on truncated wallace and dadda multiplier as basic multiplication unit K Neelima, C Padma, C Nalini, M Balaji 2023 IEEE 12th International Conference on Communication Systems and Network … , 2023 2023 Citations: 13
Smart Traffic Control System for Emergency Vehicle Clearance CP D. Aswani International Journal and Magazine of Engineering Technology Management and … , 2016 2016 Citations: 8
Efficient approximate adders for image processing applications C Padma, SB Potladurty, C Nalini, T Suguna, CH Pallavi 2024 International Conference on Advances in Computing Research on Science … , 2024 2024 Citations: 4
Post-Pandemic Biometric Challenges and Solutions: A Shocker to Supply Chain K Neelima, B Madhavi, C Padma, BK Pandey, G Gowwrii, SS Manaktala AI and Machine Learning Impacts in Intelligent Supply Chain, 196-208 , 2024 2024 Citations: 4
Efficient cached 64 point FFT processor using floating point arithmetic for OFDM application C Padma, P Jagadamba, RR Patil Instrumentation, Mesure, Metrologie 21 (1), 21 , 2022 2022 Citations: 3
Implementation of High Performance FFT Architecture for DSP Applications C.Padma, P.Jagadamba, P. Ramana Reddy International journal of Advanced Science and Technology (IJAST) 29 (No.3 … , 2020 2020 Citations: 3
Hybrid Cryptography and Steganography-Based Security System for IoT Networks T Suguna, C Padma, MJ Rani, GP Priya International journal on recent innovation trends in computing and … , 2023 2023 Citations: 2
A Review on Optimized FFT Architectures for Wireless Communication System C.Padma, P.Jagadamba, P. Ramana Reddy Journal of Advanced Research and Dynamical and Control Systems 10 (14), 1654 … , 2018 2018 Citations: 2
Smart agriculture seeding and fertilizer spray robot using IoT B Kumar, C Padma Int J Sci Eng Technol Res 6 (03), 0437-0440 , 2017 2017 Citations: 2
Post-Pandemic Economy–Shocks, Risks and Suggestive Measures K Neelima, CH Kavya, C Padma, T Suguna Economic Uncertainty in the Post-Pandemic Era, 187-197 , 2024 2024 Citations: 1
Design of a 64-bit SQRT-CSLA with reduced area and high-speed applications in low power VLSI circuits CH Pallavi, C Padma, RK Kumar, T Suguna, C Nalini arXiv preprint arXiv:2410.15736 , 2024 2024 Citations: 1
High Speed Single Precision 64-Tap FIR Filter Using Urdhva Tiryagbhyam Sutra K Neelima, M Sandhiya, C Padma, SJ Ali, KR Meruva 2024 IEEE Students Conference on Engineering and Systems (SCES), 1-5 , 2024 2024 Citations: 1
A Novel Approach for Design & Implementation of Traffic Light Controller System Using FPGA C Padma, C Pallavi International Journal for Innovative Engineering & Management Research 7 (12) , 2018 2018 Citations: 1
Comparative Analysis of 32-bit Carry look ahead Adder using ECRL and PFAL Logic CP SHAIK HIBZA INTERNATIONAL JOURNAL OF CREATIVE RESEARCH THOUGHTS - IJCRT 13 (11), 232-242 , 2025 2025
Implementation of I2C Protocol with Adaptive Baud Rate for N Number of Bits Using VERILOG CP S Aparna 2025 7th International Conference on Control Systems, Mathematical Modeling … , 2025 2025
Hardware Efficient Implementation of Image Enhancement Algorithms Using Xilinx System Generator PC Neelima Koppala, P. Rajyalakshmi, Attar Farooq Hussain, Suguna Tangimi ... 2025 International Conference on Intelligent Communication Networks and … , 2025 2025
An Efficient 32-Bit Carry Look Ahead Adder using PFAL for Low Power Circuits. CP Shaik Hibza 2025 Global Conference on Information Technology and Communication Networks … , 2025 2025
Adept Domino Logic for Modified Schmitt Trigger Circuits K Neelima, K Maheswari, SS Vali, CH Pallavi, C Padma, JA Shaik 2025 International Conference on Computing, Intelligence, and Application … , 2025 2025
DESIGN AND ANALYSIS OF PARTITION TECHNIQUE BASED DADDAMULTIPLIER ARCHITECTURE D Kalaiyarasi, T Suguna, C Padma, C Nalini, MS Raj, G Nagarajan 2025
