Dr. Parameshwara M C obtained his B.E. degree from Bangalore University in Electronics and Communication Engineering in 1999, M.Tech in Electronics Engineering from BMSCE, Bangalore, Visvesvaraya Technological University (VTU) in 2007, and obtained the Ph.D. in Electrical & Electronic Engineering Sciences from VTU, Belagavi in 2018. He joined the Department of Electronics & Communication Engineering, Vemana Institute of Technology, in 2004 as a Lecturer,. Currently, he is an Associate Professor and Head of the Department . He has over 20 years of Teaching experience in Analog Electronics, VLSI, Advanced Mixed Signal design, Linear Integrated Circuits, Microelectronics, CMOS VLSI Design, Verilog HDL, and VHDL. His Area of Specialization is VLSI, Quantum Computing, and Mixed mode VLSI Design. He has published 35 research papers in National and International conferences and Journals. He is a senior member of IEEE and life member of ISTE.
EDUCATION
BE(ECE), M.Tech(Electronics), Circuits & Systems)
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Hardware and Architecture, Multidisciplinary, Signal Processing
25
Scopus Publications
271
Scholar Citations
9
Scholar h-index
8
Scholar i10-index
Scopus Publications
Approximate Adders with Configurable Input Wiring: A Quantum-dot Cellular Automata Nanocomputing Perspective Angshuman Khan, M. C. Parameshwara, Naeem Maroof Journal of Circuits Systems and Computers, 2026 In this work, two novel low-cost approximate adder designs based on quantum-dot cellular automata (QCA) technology are introduced. The designs exploit the configuration of input bits and carry generation from the inexact lower part (LP) to the exact upper part (UP) of the adder, yielding efficient performance in terms of area and delay. When benchmarked against truncation-based adders (trun-0 and trun-1), superior performance is demonstrated, while significant area reductions are achieved in comparison to exact QCA-based adder designs. Evaluation metrics, including design area, propagation delay, mean error rate and performance within an image processing application, are employed to provide a comprehensive analysis. The experimental results suggest that the proposed designs achieve over a 60% reduction in the area-delay product relative to exact adders, exhibiting substantial benefits in terms of minimized area requirements, decreased propagation delay and improved error performance compared to previous approximate adder designs. Specifically, the proposed 8-bit adder achieves 46% and 18% area savings compared to 8-bit EXA and AXA designs, respectively. For image processing applications using 3[Formula: see text]3 low-pass filtering, the proposed designs demonstrate robust performance, with average PSNR values of 16.8[Formula: see text]dB and 18.1[Formula: see text]dB across multiple test images, providing a comprehensive evaluation of the adders’ efficacy.
Design of an Area-Efficient and Low-Power 4:2 Approximate Compressor with Improved Image Quality Metrics M. C. Parameshwara, Angshuman Khan, M. Nagabushanam IEEE Embedded Systems Letters, 2026 This paper presents a new area-efficient approximate 4-2 compressor with improved image quality and error metrics. The proposed compressor is developed using functional approximation and Karnaugh map (K-map) simplification. The circuit behavior is verified through modeling and synthesis using Verilog HDL. The effectiveness of the proposed compressor for image multiplication is evaluated using an 8 × 8 approximate multiplier simulated in MATLAB. The performance of the proposed design is compared with existing compressors using circuit, error, and image-quality metrics. Post-synthesis and image-multiplication results show that the proposed compressor achieves excellent power, delay, and image-quality performance compared to existing area-efficient designs.
A New Exact Reversible Full Adder for High Speed Arithmetic Applications Nitya S, M. C. Parameshwara, M Nagabushanam 2024 3rd International Conference for Innovation in Technology Inocon 2024, 2024 In this paper, we present a new exact reversible full adder has a ‘quantum cost’ (QC) of 9 with total delay of 7Δ. The proposed adder herein referred to as "Exact Reversible Full Adder" (ERFA). The proposed ERFA is designed using 4-Feynman gates and 1-Fredkin gate in three different stages. The proposed ERFA has ‘2’ ancillary inputs (AIs) and ‘3’ garbage outputs (GOs). Further, to verify the functionality, the proposed ERFA is designed and validated through Verilog HDL code simulation. Also, it is compared in terms of various design metrics (DMs) against 16 reversible full adders that were reported in the current literature.
Reconfigurable lower-part approximate adder with errortolerant application: an approach using QCA computing Angshuman Khan, M.C. Parameshwara, Naeem Maroof International Journal of Ad Hoc and Ubiquitous Computing, 2024 This work describes a new multi-bit approximate full adder (reconfigurable lower-part) or MAFA(RL) architecture made up of an MSB adder (exact) and an LSB adder (approximate). The MSB adder consists of a handful of 1-bit exact adders. The LSB adder is designed using majority gates with distinct configurations - OR, AND, buffer, constant-0, and constant-1 to justify the reconfigurability of the block. The QCADesigner tool is used to design and test the suggested layout. The recommended design has 4% and 13.3% fewer cell and clock phase counts than the others. The primary advantage of the proposed design is the reconfigurability of a few of its inputs. The image processing application serves as a demonstration of the fault-tolerant functionality of the design. Furthermore, an analysis of image quality metrics (IQM) and other parameters reveals an 11% and 12% improvement in the recommended block's area-delay product (ADP) and normalised ADP (NADP), respectively.
A Novel Adaptive Beamforming Technology for Mobile Communication Rekha R. S., M. C. Parameshwara, Veerendra Dakulagi IETE Journal of Research, 2024 The least mean square (LMS) beamformer is an extensively considered method in numerous mobile communication applications principally because of its computational efficiency, dynamic tracking ability, and accurate adaptive beamforming. However, this method requires huge iterations to reduce the mean square error (MSE) to zero for successful adaptive beamforming. To overcome this, we use a speeding unit (SU) device to speed up the rate of convergence of the LMS beamformer. The proposed method is named as the improved LMS (ILMS) method which provides accurate adaptive beamforming in six to seven iterations. Furthermore, we improve the proposed LMS method by applying Hanning, Hamming, and Kaiser Windows to notably curb the peak side lobe levels (PSLL). These methods are named HN-ILMS, HM-ILMS, and KB-ILMS respectively. Experimental results show that proposed HN-ILMS, HM-ILMS, and KB-ILMS give accurate adaptive beamforming with reduced PSLL.
Approximate Adders with Configurable Input Wiring: A Quantum-dot Cellular Automata Nanocomputing Perspective A Khan, N Maroof, MC Parameshwara Journal of Circuits, Systems and Computers , 2026 2026
Design of an Area-Efficient and Low-Power 4: 2 Approximate Compressor with Improved Image Quality Metrics MC Parameshwara, A Khan, M Nagabushanam IEEE Embedded Systems Letters , 2026 2026
Analysis of Modern Kalman Filter Algorithms for Radar-Based Target Tracking under Uncertainty R T K, P MC, P Lingadevaru 2025 International Conference on Vehicular Technology and Transportation … , 2025 2025 Citations: 1
Reversible quantum circuits for approximate computing with image processing application S Nitya, A Khan, MC Parameshwara, M Nagabhushanam Signal, Image and Video Processing 19 (9), 715 , 2025 2025 Citations: 4
A novel adaptive beamforming technology for mobile communication R RS, MC Parameshwara, V Dakulagi IETE Journal of Research 70 (3), 2204-2211 , 2024 2024 Citations: 1
A New Exact Reversible Full Adder for High Speed Arithmetic Applications S Nitya, MC Parameshwara, M Nagabushanam 2024 3rd International Conference for Innovation in Technology (INOCON), 1-5 , 2024 2024 Citations: 1
Reconfigurable lower-part approximate adder with error-tolerant application: an approach using QCA computing A Khan, MC Parameshwara, N Maroof International Journal of Ad Hoc and Ubiquitous Computing 46 (2), 65-79 , 2024 2024 Citations: 7
Regression-Based Approach for Paddy Crop Assists for Atmospheric Data SS Kumar, BNM Reddy, MC Parameshwara Advances in Computing and Information: Proceedings of ERCICA 2023, Volume 1 … , 2023 2023
Defects of quantum dot cellular automata computing devices: An extensive review, evaluation, and future directions A Khan, MC Parameshwara, R Arya Microprocessors and Microsystems 101, 104912 , 2023 2023 Citations: 19
Modified LMS beamformer for interference rejection RS Rekha, MC Parameshwara, V Dakulagi Wireless Personal Communications 129 (3), 2199-2211 , 2023 2023 Citations: 2
Regression-Based Approach for Paddy Crop Assists for Atmospheric Data S Sampath Kumar, BN Manjunatha Reddy, MC Parameshwara International Conference on Emerging Research in Computing, Information … , 2023 2023 Citations: 1
A novel approach for identification of healthy and unhealthy leaves using scale invariant feature transform and shading histogram-PCA techniques KS Shashidhara, H Girish, MC Parameshwara, BK Rai, V Dakulagi Emerging Research in Computing, Information, Communication and Applications … , 2022 2022 Citations: 6
Design and Analysis of 8-Bit Multiplier for Low Power VLSI Applications D Jangalwa, M Nagabushanam, MC Parameshwara 2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon), 1-5 , 2022 2022 Citations: 12
Energy estimation of QCA circuits: An investigation with multiplexers A Khan, MC Parameshwara, AN Bahar Journal of ELECTRICAL ENGINEERING(2022), 73 (4), 276–283 , 2022 2022 Citations: 7
Detection of kidney stone using digital image processing: a holistic approach A Khan, R Das, MC Parameshwara Engineering Research Express 4 (3), 035040 , 2022 2022 Citations: 18
An area-efficient majority logic-based approximate adders with low delay for error-resilient applications MC Parameshwara, N Maroof Circuits, Systems, and Signal Processing 41 (9), 4977-4997 , 2022 2022 Citations: 10
Majority logic based area-delay efficient 1-bit approximate adder for error-tolerant applications MC Parameshwara, N Maroof, A Khan Engineering Research Express 4 (2), 025033 , 2022 2022 Citations: 6
Air quality monitoring and management system model of vehicles based on the internet of things A Khan, S Chandra, MC Parameshwara Engineering Research Express 4 (2), 025014 , 2022 2022 Citations: 12
Low power pipeline-parallel phase accumulator MC Parameshwara, A Khan International Journal of Information Technology 14 (4), 1901-1908 , 2022 2022 Citations: 6
Lower-part approximate multi-bit adders for low-power DSP CV Gowdar, MC Parameshwara International Journal of Information Technology 14 (2), 731-737 , 2022 2022 Citations: 4
MOST CITED SCHOLAR PUBLICATIONS
Low-power hybrid 1-bit full-adder circuit for energy efficient arithmetic applications MC Parameshwara, HC Srinivasaiah Journal of Circuits, Systems and Computers 26 (01), 1750014 , 2017 2017 Citations: 61
Approximate full adders for energy efficient image processing applications MC Parameshwara Journal of Circuits, Systems and Computers 30 (13), 2150235 , 2021 2021 Citations: 26
Defects of quantum dot cellular automata computing devices: An extensive review, evaluation, and future directions A Khan, MC Parameshwara, R Arya Microprocessors and Microsystems 101, 104912 , 2023 2023 Citations: 19
Detection of kidney stone using digital image processing: a holistic approach A Khan, R Das, MC Parameshwara Engineering Research Express 4 (3), 035040 , 2022 2022 Citations: 18
Novel low quantum cost reversible logic based full adders for DSP applications MC Parameshwara, M Nagabushanam International Journal of Information Technology 13 (5), 1755-1761 , 2021 2021 Citations: 17
Design and Analysis of 8-Bit Multiplier for Low Power VLSI Applications D Jangalwa, M Nagabushanam, MC Parameshwara 2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon), 1-5 , 2022 2022 Citations: 12
Air quality monitoring and management system model of vehicles based on the internet of things A Khan, S Chandra, MC Parameshwara Engineering Research Express 4 (2), 025014 , 2022 2022 Citations: 12
An area-efficient majority logic-based approximate adders with low delay for error-resilient applications MC Parameshwara, N Maroof Circuits, Systems, and Signal Processing 41 (9), 4977-4997 , 2022 2022 Citations: 10
Approximate full adders for multimedia processing applications CV Gowdar, MC Parameshwara, S Sonoli 2020 IEEE International Conference for Innovation in Technology (INOCON), 1-4 , 2020 2020 Citations: 9
COMPARATIVE ANALYSIS OF VARIOUS APPROXIMATE FULL ADDERS UNDER RTL CODES CV Gowdar, MC Parameshwara, S Sonoli Journal on Microelectronics 6 (2), 947-952 , 2020 2020 Citations: 9
Reconfigurable lower-part approximate adder with error-tolerant application: an approach using QCA computing A Khan, MC Parameshwara, N Maroof International Journal of Ad Hoc and Ubiquitous Computing 46 (2), 65-79 , 2024 2024 Citations: 7
Energy estimation of QCA circuits: An investigation with multiplexers A Khan, MC Parameshwara, AN Bahar Journal of ELECTRICAL ENGINEERING(2022), 73 (4), 276–283 , 2022 2022 Citations: 7
DESIGN OF ENERGY EFFICIENT APPROXIMATE MULTIPLIERS FOR IMAGE PROCESSING APPLICATIONS CV Gowdar, MC Parameshwara Journal on Microelectronics 7 (1), 1057-1061 , 2021 2021 Citations: 7
A novel approach for identification of healthy and unhealthy leaves using scale invariant feature transform and shading histogram-PCA techniques KS Shashidhara, H Girish, MC Parameshwara, BK Rai, V Dakulagi Emerging Research in Computing, Information, Communication and Applications … , 2022 2022 Citations: 6
Majority logic based area-delay efficient 1-bit approximate adder for error-tolerant applications MC Parameshwara, N Maroof, A Khan Engineering Research Express 4 (2), 025033 , 2022 2022 Citations: 6
Low power pipeline-parallel phase accumulator MC Parameshwara, A Khan International Journal of Information Technology 14 (4), 1901-1908 , 2022 2022 Citations: 6
Design of Power Efficient 10 Bit 150 MS/s SAR-ADC in 90-nm CMOS technology M Patil, M Nagabushanam, MC Parameshwara Journal of Tianjin University Science and Technology 54 (11), 23 , 2021 2021 Citations: 6
Reversible quantum circuits for approximate computing with image processing application S Nitya, A Khan, MC Parameshwara, M Nagabhushanam Signal, Image and Video Processing 19 (9), 715 , 2025 2025 Citations: 4
Lower-part approximate multi-bit adders for low-power DSP CV Gowdar, MC Parameshwara International Journal of Information Technology 14 (2), 731-737 , 2022 2022 Citations: 4
ROBUST AND SCALABLE HYBRID 1-BIT FULL ADDER CIRCUIT FOR VLSI APPLICATIONS MC Parameshwara Journal on Microelectronics 7 (2), 1109-1114 , 2021 2021 Citations: 4