Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications Vikrant Varshney, Avaneesh K. Dubey, R. K. Nagaria Journal of Circuits Systems and Computers, 2021 The need of energy-efficient, high-speed, and low-offset analog-to-digital converters is forcing to design the dynamic latch comparators to enhance the speed and energy efficiency with minimum offset. This paper presents a novel double tail dynamic latch comparator using bulk-driven process and common-gate (CG) amplifier in amplification stage. The gain of amplification stage is enhanced using GACOBA load in which gain is controlled by bulk amplification through CG amplifier. It results in remarkable enhancement in regeneration speed and reduction in power consumption. The analytical expressions of delay and offset due to mismatch are also derived. These derivations explore the key contributors to reduce the delay and offset of proposed comparator. The outcomes are verified in CADENCE SPECTRE at 45-nm CMOS process technology through various simulations and Monte-Carlo analysis at different process corners. The post-layout analysis validates the simulation results. The proposed comparator is 93% more energy-efficient and lessens more than 84% delay in comparison of conventional design. The 1–[Formula: see text] input offset voltage and average input voltage error due to kickback noise are 2.48[Formula: see text]mV and 0.824[Formula: see text][Formula: see text]V, respectively at 0.8[Formula: see text]V power supply with 34.32[Formula: see text][Formula: see text]m2 active area.
Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit Ankur Kumar, Pratosh K. Pal, Vikrant Varshney, Avaneesh K. Dubey, R. K. Nagaria Lecture Notes in Electrical Engineering, 2021 A leakage-tolerant low-power wide fan-in OR logic domino circuit is presented to decrease the leakage current and to enhance the noise immunity. Primarily, an efficient switching control in keeper network is developed to reduce the switching of keeper transistor in both phases, so that dynamic power and noise immunity can be improved. Further, a diode-connected NMOS transistor in evaluation network is incorporated in series with the footer transistor of standard domino circuits. This significantly decreases the leakage current and charge sharing because of the stacking effect. This reduction in leakage and charge sharing ensures the improvement in the noise margin. Furthermore, a current mirror and feedback NMOS transistors are also employed in the evaluation network to improve the speed of the circuit and fully discharge the dynamic node. The simulation results of proposed domino and reported domino circuits are designed using Spectre simulator under cadence virtuoso models of 45-nm technology which shows the 31% reduction in power dissipation (PD) and 1.53 times improvement in noise immunity at the similar delay compared to the standard domino circuits.
An energy efficient 16T Hybrid-CMOS full adder using novel full swing XNOR Logic Keshav Kumar Mishra, Avaneesh K. Dubey, Vikrant Varshney, Kamal Prakash Pandey 2020 IEEE Students Conference on Engineering and Systems Sces 2020, 2020 In this paper, an energy efficient novel hybrid-CMOS 1-bit Full Adder based on XNOR-XNOR logic is presented. The proposed full adder is designed with 16 transistors, whereas the novel full swing XNOR logic is implemented using 5 transistors. The proposed hybrid full adder is designed in Cadence Virtuoso and the simulation work is carried out in Spectre simulator at $45nm$ technology node and 0.8V of power supply. The proposed work has been compared with recent reported work based on several hybrid design style. The propagation delay, power dissipation and energy consumption are 207.2pS, 45.32nW and 9.39aJ respectively for the proposed hybrid full adder. Addition to these, the effect of process and temperature variation has been analyzed. The novel full swing XNOR helps to improve the nose margin of the proposed HFA. A 4-bit binary adder is also implemented using the proposed 1-bit hybrid full adder for the purpose of test and verification. The propagation delay and power dissipation are 551pS and 168.83nW respectively for the 4-bit binary adder.
Impact of channel doping fluctuation and metal gate work function variation in FD-SOI MOSFET for 5nm BOX Thickness Avaneesh K. Dubey, Pratosh K. Pal, Vikrant Varshney, Ankur Kumar, R. K. Nagaria 2019 IEEE Conference on Information and Communication Technology Cict 2019, 2019 This study presents the behavior of fully depleted silicon-on-insulator (FD-SOI) MOSFET by variation of channel doping concentration and work function of gate material. The channel doping concentration and work function of gate material are varied from 1012to 1019 cm-3and 4.4 to 4.8eV respectively. The investigation is presented for 5nm of silicon film thickness with 2nm and 5nm thickness of gate oxide and buried oxide (BOX) respectively. The comparative study of doping variation on several performance parameters has been characterized using Visual TCAD EDA Tool. The result shows that there is very sharp rise or fall in the device parameters value at very high doping (1019 cm-3), The required tuning of off current is also possible with respect to these variations as the 81 % sudden drop is noticed for 10 times increment in doping concentration from 1017 cm-3and at work function of 4.6eV.
Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage Avaneesh K. Dubey, R. K. Nagaria Analog Integrated Circuits and Signal Processing, 2019 This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and power-efficient data conversion. The amplification stage of the proposed DTDC is designed using self-biasing technique, which helps to reduce external biasing requirement to bias bulk/gate of the transistors. The self-biasing technique controls threshold voltage (Vth) of the transistors either for fast switching (low-Vth) or for low power dissipation (high-Vth). The latch stage of the proposed DTDC is designed with novel dynamic CMOS inverters to improve the regeneration speed. The mathematical equations for delay and offset voltage are derived for the proposed DTDC and improvements are mentioned. The proposed DTDC is designed in CADENCE and simulated with SPECTRE using 45 nm CMOS process technology at the low power supply of 0.8 V to verify the outcomes. The simulation results reveal that the delay and power dissipation of the proposed DTDC are 166.29 pS and 2.3 µW respectively. The analysis of 1-sigma offset error is performed using Monte-Carlo simulation. Here, the mismatch and process variation are considered and the samples are generated randomly till 200 samples (runs). Additionally, the peak input voltage error due to kickback noise is 0.219 mV for a differential input voltage of 5 mV.
A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator for Low-Voltage Applications Vikrant Varshney, Ankur Kumar, Avaneesh Kumar Dubey, Priyanka Singh, R. K. Nagaria Proceedings 2019 International Conference on Electrical Electronics and Computer Engineering Upcon 2019, 2019 This paper presents an energy-efficient low-voltage double-tail dynamic latch comparator which shows high switching speed in comparison to conventional design. The proposed comparator is designed using improved pre-amplifier stage in which hybrid design style is adopted to enhance latch speed with optimum power. As a result, energy efficiency is improved. The analytical expressions for delay calculation are also derived for the proposed comparator. The rigorous simulations are analyzed in CADENCE SPECTRE at 90nm CMOS technology with 1V power supply. The mismatch analysis for offset voltage is validated using Monte-Carlo simulations at 200 samples. The simulations and analytical derivations corroborate that the enhanced speed is achieved with low-offset and optimized power dissipation. The simulation results confirm that the proposed design is about 2 times faster, 52.89% more energy efficient, and minimizes 27.51% offset voltage in contrast of conventional dynamic comparator at the cost of $20.39\\mu\\mathrm{W}$ power consumption and $54.03\\mu \\mathrm{m}^{2}$ active die area.
Design and Analysis of Noise Immune, Energy Efficient 1-bit 8T SRAM Cell H Shivhare, AK Dubey, SK Jha International Conference on VLSI, Communication and Signal processing, 465-473 , 2022 2022 Citations: 1
Design and performance of high-speed energy-efficient CMOS double tail dynamic latch comparator using GACOBA load suitable for low voltage Applications V Varshney, AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 30 (11), 2150191 , 2021 2021 Citations: 3
Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit A Kumar, PK Pal, V Varshney, AK Dubey, RK Nagaria Advances in VLSI, Communication, and Signal Processing: Select Proceedings … , 2020 2020 Citations: 3
Design and Performance of High-Speed CMOS Double-Tail Dynamic Comparator Suitable for Mixed-Signal ICs AK Dubey, V Varshney, A Kumar, PK Pal, RK Nagaria Advances in VLSI, Communication, and Signal Processing: Select Proceedings … , 2020 2020 Citations: 2
A 0.18 µm β-Ga 2 O 3 MOSFET Using Al 2 O 3 /HfO 2 /SiO 2 Gate Dielectric for Low- V TH High-Power Electronics Applications PK Pal, AK Dubey, RK Chauhan, RK Nagaria International Conference on VLSI, Communication and Signal processing, 1009-1016 , 2020 2020
Low-Power Enhanced Speed Two-Tail Dynamically Controlled Comparator Suitable for Subthreshold CMOS Circuits AK Dubey, V Varshney, A Kumar, PK Pal, RK Nagaria International Conference on VLSI, Communication and Signal processing, 1121-1135 , 2020 2020 Citations: 1
An Energy Efficient 16T Hybrid-CMOS Full Adder using Novel Full Swing XNOR Logic KK Mishra, AK Dubey, V Varshney, KP Pandey 2020 IEEE Students Conference on Engineering & Systems (SCES), 1-6 , 2020 2020 Citations: 10
Impact of Channel Doping Fluctuation and Metal Gate Work Function Variation in FD-SOI MOSFET for 5nm BOX Thickness AK Dubey, PK Pal, V Varshney, A Kumar, RK Nagaria 2019 IEEE Conference on Information and Communication Technology, 1-4 , 2019 2019 Citations: 5
A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator for Low-Voltage Applications V Varshney, A Kumar, AK Dubey, P Singh, RK Nagaria 2019 International Conference on Electrical, Electronics and Computer … , 2019 2019 Citations: 3
Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 28 (09), 1950157 , 2019 2019 Citations: 13
Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage AK Dubey, RK Nagaria Analog Integrated Circuits and Signal Processing, 1-11 , 2019 2019 Citations: 44
Design and Performance of High-speed Low-Offset CMOS Double-Tail Dynamic Comparators using Offset Control scheme AK Dubey, PK Pal, V Varshney, A Kumar, RK Nagaria 2019 9th Annual Information Technology, Electromechanical Engineering and … , 2019 2019 Citations: 10
A 0.55V, 28.6ppm/ ◦ C Nanopower Subthreshold Voltage Reference with Body Biasing PK Pal, AK Dubey, A Kumar, V Varshney, RK Nagaria 2018 15th IEEE India Council International Conference (INDICON), 1-6 , 2018 2018
Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 27 (13), 1850204 , 2018 2018 Citations: 19
A Modified High Speed Domino with Low Leakage for Wide Fan-in Domino OR-Gate Ankur Kumar, Pratosh Kumar Pal, Avaneesh Kumar Dubey, Vikrant Varshney, R K ... 2018 15th IEEE India Council International Conference (INDICON) - Circuits … , 2018 2018 Citations: 3
Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process V Varshney, AK Dubey, A Kumar, PK Pal, RK Nagaria 2018 3rd International Innovative Applications of Computational Intelligence … , 2018 2018 Citations: 15
Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load AK Dubey, RK Nagaria Microelectronics Journal 78 (August 2018), 1-10 , 2018 2018 Citations: 55
Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure R Jain, AK Dubey, V Varshney, RK Nagaria 2017 4th IEEE Uttar Pradesh Section International Conference on Electrical … , 2017 2017 Citations: 21
Voltage comparison based high speed & low power domino circuit for wide fan-in gates PK Pal, AK Dubey, SR Kassa, RK Nagaria 2016 IEEE International Conference on Electron Devices and Solid-State … , 2016 2016 Citations: 12
Enhanced slew rate, constant-g m rail-to-rail OpAmp using 1:2 current mirror biasing technique AK Dubey, RK Nagaria, PK Pal, RK Singh 2016 International Conference on Computing, Communication and Automation … , 2016 2016 Citations: 7
MOST CITED SCHOLAR PUBLICATIONS
Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load AK Dubey, RK Nagaria Microelectronics Journal 78 (August 2018), 1-10 , 2018 2018 Citations: 55
Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage AK Dubey, RK Nagaria Analog Integrated Circuits and Signal Processing, 1-11 , 2019 2019 Citations: 44
Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure R Jain, AK Dubey, V Varshney, RK Nagaria 2017 4th IEEE Uttar Pradesh Section International Conference on Electrical … , 2017 2017 Citations: 21
Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 27 (13), 1850204 , 2018 2018 Citations: 19
Design of Power Efficient Low-Offset Dynamic Latch Comparator using 90nm CMOS Process V Varshney, AK Dubey, A Kumar, PK Pal, RK Nagaria 2018 3rd International Innovative Applications of Computational Intelligence … , 2018 2018 Citations: 15
Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 28 (09), 1950157 , 2019 2019 Citations: 13
Voltage comparison based high speed & low power domino circuit for wide fan-in gates PK Pal, AK Dubey, SR Kassa, RK Nagaria 2016 IEEE International Conference on Electron Devices and Solid-State … , 2016 2016 Citations: 12
An Energy Efficient 16T Hybrid-CMOS Full Adder using Novel Full Swing XNOR Logic KK Mishra, AK Dubey, V Varshney, KP Pandey 2020 IEEE Students Conference on Engineering & Systems (SCES), 1-6 , 2020 2020 Citations: 10
Design and Performance of High-speed Low-Offset CMOS Double-Tail Dynamic Comparators using Offset Control scheme AK Dubey, PK Pal, V Varshney, A Kumar, RK Nagaria 2019 9th Annual Information Technology, Electromechanical Engineering and … , 2019 2019 Citations: 10
Enhanced slew rate, constant-g m rail-to-rail OpAmp using 1:2 current mirror biasing technique AK Dubey, RK Nagaria, PK Pal, RK Singh 2016 International Conference on Computing, Communication and Automation … , 2016 2016 Citations: 7
Efficient technique to reduce power dissipation of Op-Amps at high speed AK Dubey, P Srivastava, M Pattanaik 2015 International Conference on Robotics, Automation, Control and Embedded … , 2015 2015 Citations: 7
Impact of Channel Doping Fluctuation and Metal Gate Work Function Variation in FD-SOI MOSFET for 5nm BOX Thickness AK Dubey, PK Pal, V Varshney, A Kumar, RK Nagaria 2019 IEEE Conference on Information and Communication Technology, 1-4 , 2019 2019 Citations: 5
Design and performance of high-speed energy-efficient CMOS double tail dynamic latch comparator using GACOBA load suitable for low voltage Applications V Varshney, AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 30 (11), 2150191 , 2021 2021 Citations: 3
Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit A Kumar, PK Pal, V Varshney, AK Dubey, RK Nagaria Advances in VLSI, Communication, and Signal Processing: Select Proceedings … , 2020 2020 Citations: 3
A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator for Low-Voltage Applications V Varshney, A Kumar, AK Dubey, P Singh, RK Nagaria 2019 International Conference on Electrical, Electronics and Computer … , 2019 2019 Citations: 3
A Modified High Speed Domino with Low Leakage for Wide Fan-in Domino OR-Gate Ankur Kumar, Pratosh Kumar Pal, Avaneesh Kumar Dubey, Vikrant Varshney, R K ... 2018 15th IEEE India Council International Conference (INDICON) - Circuits … , 2018 2018 Citations: 3
Design and Performance of High-Speed CMOS Double-Tail Dynamic Comparator Suitable for Mixed-Signal ICs AK Dubey, V Varshney, A Kumar, PK Pal, RK Nagaria Advances in VLSI, Communication, and Signal Processing: Select Proceedings … , 2020 2020 Citations: 2
Low Power, Accurate Variable Gain Amplifier (VGA) with High dB-Linear Gain at 900 MHz AK Dubey, P Srivastava, M Pattanaik International Journal on Advance Research in Electrical and Electronics … , 2015 2015 Citations: 2
Design and Analysis of Noise Immune, Energy Efficient 1-bit 8T SRAM Cell H Shivhare, AK Dubey, SK Jha International Conference on VLSI, Communication and Signal processing, 465-473 , 2022 2022 Citations: 1
Low-Power Enhanced Speed Two-Tail Dynamically Controlled Comparator Suitable for Subthreshold CMOS Circuits AK Dubey, V Varshney, A Kumar, PK Pal, RK Nagaria International Conference on VLSI, Communication and Signal processing, 1121-1135 , 2020 2020 Citations: 1
