Design and implementation of dual-core MIPS processor for LU decomposition based on FPGA Rusul Khalil Saad, Safaa S. Omran International Journal of Electrical and Computer Engineering, 2021 Many systems like the control systems and in communication systems, there is usually a demand for matrix inversion solution. This solution requires many operations, which makes it not possible or very hard to meet the needs for real-time constraints. Methods were exists to solve this kind of problems, one of these methods by using the LU decomposition of matrix which is a good alternative to matrix inversion. The LU matrices are two matrices, the L matrix, which is a lower triangular matrix, and the U matrix, which is an upper triangular matrix. In this paper, a design of dual-core processor is used as the hardware of the work and certain software was written to enable the two cores of the dual-core processor to work simultaneously in computing the value of the L matrix and U matrix. The result of this work are compared with other works that using single-core processor, and the results found that the time required in the cores of the dual-core is more less than using single-core. The designed dual-core processor is invoked using the VHDL language.
Cache coherency controller for MESI protocol based on FPGA Mays K. Faeq, Safaa S. Omran International Journal of Electrical and Computer Engineering, 2021 In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So if one core requestes a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores.This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using very high speed integrated circuit hardware description language (VHDL) coding and implemented using ISE Xilinx software. The protocol used in this design is the modified, exclusive, shared and invalid (MESI) protocol. Test results were taken by using test bench, and showed all the states of the protocol are working correctly.
Hybrid branch prediction for pipelined MIPS processor Ali S. Al-Khalid, Safaa S. Omran International Journal of Electrical and Computer Engineering, 2020 In the modern microprocessors that designed with pipeline stages, 
 the performance of these types of processors will be affected when executing branch instructions, because in this case there will be stalls in the pipeline. In turn this causes in reducing the Cycle Per Instruction (CPI) of the processor. In the case of executing a branch instruction, the processor needs an extra clocks to know if that branch will happen (Taken) or not (Not Taken) and also it requires calculating the new address in the case of the branch is Taken. The prediction that the branch is T / NT is an important stage in enhancing the processor performance. In this research more than one method of branch prediction (hybrid) is used and the designed circuit will choose different types of prediction algoritms depending on the type of the branch. Some of these methods were used are static while the other are dynamic. All circuits were built practically and examined by applying different programs on the designed predictor algorithm to compute the performance of the processor.
Ultra fast frequency independent instantaneous power factor detector Safaa S. Omran, Ali. Sh. Al-Khalid, Amer Atta Yaseen International Journal of Power Electronics and Drive Systems, 2019 Many schemes were attempted to lessenthe time taken for measuring the power factor of a linear load. This paper suggests taking advantage of a previous paper where only two samples of the voltage and current were adequate to have a very fast calculation method of the power factor. That scheme used a phase locked loop (PLL) as a frequency multiplier scheme to acquire two progressive samples of the voltage and current which are concurrent. The time elapsed for measurement was the reciprocal of the PLL sampling frequency; no further scheme was reported after that to claim a faster method. This paper gets use of that work to get two progressive samples of voltage and current separated by a short time. The scheme is frequency independent with an indication for lead lag. All the operations are executed by a PIC microcontroller rather than a computer with few support circuits. The output will be shown either in digital or analogue (DC) form. The percentage of error depends mainly on the resolution (number of bits) for both the ADC and DAC used.
A shortest data window algorithm for detecting the power factor in presence of non-sinusoidal load current Safaa S. Omran, Ali Sh. Al-Khalid, Amer Atta Yaseen International Journal of Electrical and Computer Engineering, 2019 During recent years, nonlinear power electronic equipments introduce harmonic pollution on electric power systems. It makes the traditional power factor meter can not act accurately when it monitors unbalanced and harmonic loads. In this paper, a new algorithm for detecting the power factor in presence of non-sinusoidal load current is proposed. The proposed algorithm detects the true power factor exactly. By uses only two successive sampled data points of the voltage and the current for each displacement power factor value calculation and two sampled data points for each distortion power factor value calculation, the total/true power factor becomes easy to measure using these values directly. The proposed detector implemented using microcontroller as a main part and has been tested for single phase power system. The test results show that it can measure the true power factor of the loads quickly and accurately.
Selective branch prediction schemes based on FPGA MIPS processor for educational purposes H S Mahmood, S S Omran Iop Conference Series Materials Science and Engineering, 2019 Abstract Processor performance is measured by amount of ILP (Instruction Level Parallelism) represented by its design. this parallelism is limited by the execution of conditional branch instructions which may break the flow of the program execution. To overcome this problem, several ways were suggested in order to predict both the direction of instructions execution and the address of the instruction to be executed next. In this paper, a design for a dynamic branch predictor was implemented in VHDL (VHSIC Hardware Description Language) then it was integrated with FPGA (Field Programmable Gate Arrays) MIPS (Microprocessor without Interlocked Pipelined Stages) processor and its ability to increase prediction accuracy and MIPS processor performance was approved. This predictor combines gshare and bimodal branch prediction techniques by dividing the PHT (Pattern History Table) into two branch streams corresponding to taken and not-taken states. This combined branch predictor was synthesized using the XILINX ISE (Integrated Software Environment) Design Suite 14.7 tool.
Fast QR Decomposition Based on FPGA Safaa S. Omran, Ahmed K. Abdul-abbas Icoase 2018 International Conference on Advanced Science and Engineering, 2018 The QR-decomposition (QRD) is an implementation necessary for many different detection algorithms such as MIMO (Multiple Input and Multiple Output) in wireless communication system. In this article, a QRD processor which decomposes the matrix into an orthogonal (Q matrix) and upper triangular matrix (R matrix) using Gram Schmidt algorithm is designed and implemented using a 32-bit High speed processor based on FPGA. This design requires 16 clock cycle to compute QR decomposition with 15.625 M QRDs per second throughput at 250 MHz operating frequency.
Implementation of LRU Replacement Policy for Reconfigurable Cache Memory Using FPGA Safaa S. Omran, Ibrahim A. Amory Icoase 2018 International Conference on Advanced Science and Engineering, 2018 Cache memory is an important part in computer systems. In set associative cache memory each incoming memory block from the main memory into cache memory should be placed in one of many specific cache lines according to the degree of associativity. In case of all ways lines are fill, a replacement policy should be designed to indicate which line of that cache memory ways will be replaced. In this paper a LRU (Least Recently Used) replacement policy has been implemented in two different methods for reconfigurable cache memory using FPGA (Field-Programmable Gate Array) and programmed using VHDL (Very high speed IC Hardware Description Language). The tree based pseudo LRU replacement policy is much simple and requires less LRU array size than Conventional LRU because it needs only 7 bits for each cache line. While the conventional LRU is easier in implemented and also require only one unit to managing the LRU replacement policy.
Comparative Study between Different Rectangle Iris Templates Safaa S. Omran, Aqeel A. Al-Hilali Icoase 2018 International Conference on Advanced Science and Engineering, 2018 The iris recognition is the best biometric method that used today for distinguish between users. The iris recognition system is providing to distinguish between human based on unique features located inside irises. Ridge-Energy-Direction (RED) algorithm is used for extracting iris features from the rectangle iris template. This research presents comparative between four different ways of choosing iris region of human or identifications and tries to locate the best way among them. These ways are tested on two different databases (CASIA V1 and CASIA Interval). A full design of iris recognition system is made from segmentation, normalization, features extraction, and matching to test these rectangle iris templates. This paper recommends choosing the iris region that near to the pupil likes quarter iris region template, since this iris region template has small sizes among other templates in terms of pixels and gives 100% accuracy in identification and verification.
Design and implementation of 32-Bits MIPS processor to Perform QRD Based on FPGA Safaa S. Omran, Ahmed K. Abdul-abbas International Iraqi Conference on Engineering Technology and Its Applications Iiceta 2018, 2018 The QR decomposition (QRD) is an important prerequisite for many different applications such as multiple input multiple output (MIMO) detection in wireless communication system, matrix inversion, radar application and so on. This paper presents the design and implementation of a 32-bit MIPS (Microprocessor without Interlocked Pipeline Stage) processor based on QRD using Givens Rotation algorithm. Moreover, this design contains a developed hardware in order to reduce the latency of QRD process. The implementation results of this QRD processor are compared with another work. Finally, design, synthesis of this QRD processor has been achieved using Xilinx 14.7 ISE simulator and coding is written in Verilog HDL language and implemented on Virtex - 7 FPGA (Field Programmable Gate Array) kit.
Iraqi car license plate recognition using OCR Safaa S. Omran, Jumana A. Jarallah 2017 Annual Conference on New Trends in Information and Communications Technology Applications Ntict 2017, 2017
Using genetic algorithm to cryptanalyse a simple substitution cipher 11th Middle Eastern Simulation Multiconference Mesm 2010 1st Gameon Arabia Conference Gameon Arabia 2010, 2010
Design and implementation of an intelligent autonomous robot system International Conference on Automation Robotics and Control Systems 2008 Arcs 2008, 2008
Microcomputer-controlled sampling acoustic meter Modelling Simulation Control B, 1990
FAST CAMERA INTERFACE. Electronics Wireless World, 1985
RECENT SCHOLAR PUBLICATIONS
Design and implementation of dual-core mips processor for lu decomposition based on fpga RS Khalil, SS Omran International Journal of Electrical and Computer Engineering (IJECE) 11 (2 … , 2021 2021 Citations: 1
Cache coherency controller for MESI protocol based on FPGA MK Faeq, SS Omran International Journal of Electrical and Computer Engineering 11 (2), 1043 , 2021 2021 Citations: 5
Hybrid branch prediction for pipelined MIPS processor AS Al-Khalid, SS Omran International Journal of Electrical and Computer Engineering 10 (4), 3476 , 2020 2020 Citations: 1
Design and Implementation of MIPS Processor for LU Decomposition based on FPGA RS Khalil, SS Omran European Journal of Electrical Engineering and Computer Science 4 (3) , 2020 2020 Citations: 1
Ultra fast frequency independent instantaneous power factor detector SS Omran, AS Al-Khalid, AA Yaseen International Journal of Power Electronics and Drive Systems 10 (4), 1961 , 2019 2019
A shortest data window algorithm for detecting the power factor in presence of non-sinusoidal load current SS Omran, AS Al-Khalid, AA Yaseen International Journal of Electrical and Computer Engineering 9 (5), 3956 , 2019 2019
Selective branch prediction schemes based on FPGA MIPS processor for educational purposes HS Mahmood, SS Omran IOP Conference Series: Materials Science and Engineering 518 (4), 042008 , 2019 2019 Citations: 3
Comparative Study Between Different Rectangle Iris Templates SS Omran, AA Al-Hilali 2018 International Conference on Advanced Science and Engineering (ICOASE), 7-12 , 2018 2018 Citations: 1
Fast QR decomposition based on FPGA SS Omran, AK Abdul-Abbas 2018 International Conference on Advanced Science and Engineering (ICOASE … , 2018 2018 Citations: 7
Implementation of LRU replacement policy for reconfigurable cache memory using FPGA SS Omran, IA Amory 2018 International Conference on Advanced Science and Engineering (ICOASE … , 2018 2018 Citations: 16
Automatic IRAQI cars number plates extraction S Omran, J Jarallah Iraqi Journal for Computers and Informatics 44 (1), 23-30 , 2018 2018 Citations: 9
Design of 32-bits RISC processor for hardware efficient QR decomposition SS Omran, AK Abdul- abbas 2018 International Conference on Advances in Sustainable Engineering and … , 2018 2018 Citations: 9
Design and implementation of 32-Bits MIPS processor to Perform QRD Based on FPGA SS Omran, AK Abdul-abbas 2018 International Conference on Engineering Technology and their … , 2018 2018 Citations: 9
Implementation of 4-way superscalar hash MIPS processor using FPGA SS Omran, LF Jumma Journal of Physics: Conference Series 1003 (1), 012037 , 2018 2018 Citations: 2
Implementation QR decomposition based on triangular systolic array S Omran, AK Abdul-Abbas Int. J. New Technol. Sci. Eng 5 (6), 150-161 , 2018 2018 Citations: 2
Multi core processor for QR decomposition based on FPGA SS Omran, AK Abdul-abbas International Journal of Engineering & Technology 7 (4), 2100-2105 , 2018 2018 Citations: 1
Design and implementation of high speed arithmetic processor SS Omran, AK Abdul-abbas International Journal of Applied Engineering Research 13 (11), 9167-9171 , 2018 2018 Citations: 2
Iraqi license plate localization and recognition system using neural network SS Omran, JA Jarallah 2017 Second Al-Sadiq International Conference on Multidisciplinary in IT and … , 2017 2017 Citations: 13
Reconfigurable cache memory architecture design based on VHDL SS Omran, IA Amory 2017 International Conference on Electrical and Computing Technologies and … , 2017 2017 Citations: 1
Design of multithreading SHA-1 & SHA-2 MIPS processor using FPGA SS Omran, LF Jumma 2017 8th International Conference on Information Technology (ICIT), 632-637 , 2017 2017 Citations: 7
MOST CITED SCHOLAR PUBLICATIONS
Iraqi Car License Plate Recognition Using OCR SS Omran, JA Jarallah NTICT, 298-303 , 2017 2017 Citations: 45
A cryptanalytic attack on Vigenère cipher using genetic algorithm SS Omran, AS Al-Khalid, DM Al-Saady 2011 IEEE Conference on Open Systems, 59-64 , 2011 2011 Citations: 38
Using genetic algorithm to break a mono-alphabetic substitution cipher SS Omran, AS Al-Khalid, DM Al-Saady 2010 IEEE Conference on Open Systems (ICOS 2010), 63-67 , 2010 2010 Citations: 28
Implementation of LRU replacement policy for reconfigurable cache memory using FPGA SS Omran, IA Amory 2018 International Conference on Advanced Science and Engineering (ICOASE … , 2018 2018 Citations: 16
Quarter of Iris Region Recognition Using the RED Algorithm SS Omran, AA Al-Hillali 2015 17th UKSim-AMSS International Conference on Modelling and Simulation … , 2015 2015 Citations: 14
Iraqi license plate localization and recognition system using neural network SS Omran, JA Jarallah 2017 Second Al-Sadiq International Conference on Multidisciplinary in IT and … , 2017 2017 Citations: 13
Using genetic algorithms to break a simple transposition cipher AS Al-Khalid, SS Omran, DA Hammood 6th International conference on information technology ICIT , 2013 2013 Citations: 12
ECG Rhythm Analysis by Using Neuro-Genetic Algorithms SS Omran, SMR Taha, NA Awadh MASAUM Journal of Basic and Applied Sciences 1 (3) , 2009 2009 Citations: 12
Automatic IRAQI cars number plates extraction S Omran, J Jarallah Iraqi Journal for Computers and Informatics 44 (1), 23-30 , 2018 2018 Citations: 9
Design of 32-bits RISC processor for hardware efficient QR decomposition SS Omran, AK Abdul- abbas 2018 International Conference on Advances in Sustainable Engineering and … , 2018 2018 Citations: 9
Design and implementation of 32-Bits MIPS processor to Perform QRD Based on FPGA SS Omran, AK Abdul-abbas 2018 International Conference on Engineering Technology and their … , 2018 2018 Citations: 9
design of sha-1 &sha-2 mips processor using fpga safaa s omran, L jumma NTICT, 268-273 , 2017 2017 Citations: 9
Design of two dimensional reconfigurable cache memory using FPGA SS Omran, IA Amory 2016 5th International Conference on Electronic Devices, Systems and … , 2016 2016 Citations: 9
Design and implementation of multi-model biometric identification system SS Omran, MA Salih International Journal of Computer Applications 99 (15), 14-21 , 2014 2014 Citations: 9
Hardware modelling of a 32-bit, single cycle RISC processor using VHDL SS Omran, HS Mahmood ICIT 2013 The 6th International Conference on Information Technology , 2013 2013 Citations: 9
Fast QR decomposition based on FPGA SS Omran, AK Abdul-Abbas 2018 International Conference on Advanced Science and Engineering (ICOASE … , 2018 2018 Citations: 7
Design of multithreading SHA-1 & SHA-2 MIPS processor using FPGA SS Omran, LF Jumma 2017 8th International Conference on Information Technology (ICIT), 632-637 , 2017 2017 Citations: 7
Half Iris Matching Based On Red Algorithm SS Omran, AA AI-Hillali International Journal of Informatics and Communication Technology (IJ-ICT) 5 … , 2016 2016 Citations: 6
FPGA Implementation of MIPS RISC Processor for Educational Purposes SS Omran, AJ Ibada Journal of Babylon University/Pure and Applied Sciences 24 (7), 1745-1761 , 2016 2016 Citations: 6
Using an FPGA to Accelerate Iris Recognition SS Omran, A Al-Hilali ICSCME'2015, 55-62 , 2015 2015 Citations: 6
