Ujwala Anil Kshirsagar

@sitpune.edu.in

Associate Professor, Department of Electronics and Tele communication Engineering, Symbiosis Institute of Technology, Pune
Symbiosis Institute of Technology,Pune

Ujwala Anil Kshirsagar


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https://researchid.co/ujwala.kshirsagar
Ujwala A. Kshirsagar is an Associate Professor skilled in IoT, VLSI and Embedded
System Design. A life-long learner with a strong educational background holding
Master’s Degrees M.E. Digital Electronics and Ph.D. in VLSI Technology from Sant
Gadge Baba Amravati University, Amravati, India.
She is currently working as an Associate Professor in the Department of Electronics
and Tele Communication from March 2020 at Symbiosis International University,
India. Before that she was the Professor and Dean at H.V.P. M’s College of Engineering
and Technology, Amaravati, India since from 2003. She is a distinguished academician
with past 20 years of experience as a researcher and her areas of research include IoT,
VLSI & Embedded system design and micro/nano electronics manufacturing. She has
worked on different analog and digital applications using VLSI Technology, Electronics
health care applications using IoT and Embedded systems.
Completed 6 funding projects in the field of Nano electronics.

EDUCATION

ME Digital Electronics, Ph. D. Electronics Engineering

RESEARCH INTERESTS

VLSI and Embedded System Design

GRANT DETAILS

1 Fabrication and characterization of Silicon based memristor using TiO2.
Govt. of India &MCIT under INUP
28 April 2015 30 July
2016 Complete physical infrastructure, material, Nano fabrication facility along with TA/DA for one year
Successfully completed.
Patent filed. Paper published.
2 Fabrication and characterization of HfOx based RRAM synaptic cell.
Govt. of India &MCIT under INUP
11 April 2016- May 2016 Complete physical infrastructure, material, Nano fabrication facility along with TA/DA for one year
Successfully completed.
. Paper presented in IEEE Conference at Bangalore.
3 Fabrication and characterization of vertical GAA nano-pillar p-TFET transistor
Govt. of India &MCIT under INUP
11 April
2016 May 2017 Complete physical infrastructure, material, Nano fabrication facility along with TA/DA for one year
Successfully completed.

4 Characterization and fabrication of vertical nano pilar MOS ReRAM cell.
India &MCIT under INUP
11 April 2016- May 2017 Complete physical infrastructure, material, Nano fabrication facility along with TA/DA for one year
Partially completed. Report submitted.
5 Environment controlled automated Green house for high valued agro produce in Vidarbha region IIT , Delhi July 2019 -July 2020 1.5 Lakhs Successfully completed.

6 A2K Grant for International Conference on Recent and Future Trends in Electronics System Design and Manufacturing DSIR, New Delhi May 2022 -May 2023 2.6 Lacs Successfully Completed

RESEARCH OUTPUTS (PATENTS, SOFTWARE, PUBLICATIONS, PRODUCTS)

01 Power efficient phase locked loop with four multiple outputs using 45nm CMOS technology Dr. Ujwala Belorkar (Kshirsagar) 313/MUM/2011 IP India Granted in November 2022
02 6x6 memristor based Memory Dr. Ujwala Belorkar (Kshirsagar) TEMP/E-1/44983 /2016-MUM IP India Final result awaited
03 Automation of nutrient supply based smart system for multilevel hydroponic farming and method
thereof Dr. Ujwala Belorkar (Kshirsagar)
202221026711 IP India Published

INDUSTRY EXPERIENCE

ZARNA Instuments Company

1st july 1999 TO
7th December 2005
6Yr. 5 Months
Electronics Engineer