Jeetendra Singh

Scopus Publications

Design and Implementation of 16-bit FPGA-Based True Random Number Generator Using Self-Timed Ring for Aerospace Applications
Journal of Aeronautics Astronautics and Aviation, 2026
Radiations Effects on Advanced Multi-gate 3D Devices and Materials
Raj Kumar, Vakkalakula Bharath Sreenivasulu, Jeetendra Singh, Shashi Bala
Transactions on Electrical and Electronic Materials, 2025
Design and Image Encryption Implementation of High Performance and Resource-Efficient AES-128 Encryption Architecture
Deepika Ben Thakor, Jeetendra Singh, Balwinder Raj
Iciis 2025 Next Gen Engineering for Industry 5 0 Innovating Intelligent Systems for Human Centric Future Proceedings of 2025 IEEE 19th International Conference on Industrial and Information Systems, 2025
This paper presents an optimized hardware implementation of the Advanced Encryption Standard (AES-128) encryption algorithm, specifically designed to minimize resource consumption while achieving high throughput. Key optimizations include a fully parallel SubBytes operation utilizing 16 simultaneous S-boxes, runtime key derivation, and a loop-iterated architecture for round execution. This approach enhances processing speed while maintaining hardware efficiency. Functional correctness was rigorously verified using the NIST FIPS-197 standard test vectors, confirming reliable encryption and decryption for all specified cases. The implemented AES architecture achieves a throughput of 4.92 Gbps at 384.6 MHz on a Xilinx Artix-7 FPGA, encrypting 128-bit blocks in 11 clock cycles. Post-synthesis results demonstrate exceptional resource efficiency: utilization rates were 2.14% for Slice LUTs, 1.05% for registers, and 13.7% for BRAM. I/O utilization reached 96.25%, underscoring the design’s compact footprint. To demonstrate practical application, the design was adapted for image processing, successfully encrypting and decrypting a 128×128 pixel grayscale image. The encrypted output exhibited characteristic random noise, while the decrypted image perfectly reconstructed the original. These findings validate the design’s suitability for deploying AES-128 on FPGAs in secure, real-time embedded systems, IoT devices, and defense communication networks.
CWT based Fetal ECG signal analysis in terms of R-peaks detection
Anirudh Chaturvedi, Niranjan Kumar, Varun Gupta, Vivek Kumar, Jeetendra Singh
3rd International Conference on Microwave Antenna and Communication Mac 2025, 2025
This paper presents a novel approach for fetal Electrocardiogram (FECG) signal analysis, focusing on accurate R-peak detection using the Continuous Wavelet Transform (CWT). The proposed method leverages the multi-resolution capabilities of CWT to process abdominal ECG signals, enabling precise time-frequency localization for isolating fetal R-peaks. Wavelet thresholding enhances signal clarity and reduces noise, ensuring robust performance in noisy conditions. The approach demonstrates consistent accuracy and F1-score of above 90%, showcasing its effectiveness in non-invasive prenatal monitoring. Despite its computational demands, the method significantly improves the reliability of fetal cardiac analysis, offering a valuable tool for diagnosing and monitoring fetal health.
Improvement in the sensing performance of SiGe pocket Si/Ge VTFET based biosensor using extended source electrode and nano-cavity length
Jeetendra Singh, Shailendra Singh
Materials Science and Engineering B, 2024
In this work, the sensing speed and sensitivity of the dielectric modulated biosensors has been enhanced by incorporating novel approach of source over electrode extension and nano cavity length extension in the SiGe p+ pocket doped Si/Ge vertical TFET , which is named Hetero-Junction Extended Source Electrode Vertical TFET (HJ-ESE-VTEFT). In this regard, the limit of material solubility is overcome by depositing extended electrode over the Ge source and the band gap modulation at the source channel interface is performed by formation of hetero junction due to P+ pocket of SiGe material. Band gap modulation causes band narrowing and results in high speed. On the application of negative bias on the extended source electrode attracts holes from the P+ Ge source and work as add-on in the band narrowing by enhancing the abruptness at the interface. The cavity length, which was initially under the gate electrode is further extended under the source electrode provide larger area to accommodate larger bio-molecules in the cavity through the electrostatic behavior of the device can be changed. In combination, p+ SiGe pocket, Ge Source, Extended source electrode, and extended cavity length give significant improvement in the sensing speed and sensing capabilities of the device. The electrostatic characteristics and then device sensitivity of the conventional VTFET and proposed device are compared to prove the effectiveness of the proposed device. There is an increment of two-order in drain current for the neutral bio-molecules and three-order increment in the charged bio-molecule having dielectric constant of k = 5 has been noticed in the results. The proposed device produces 5.5 times higher bio-molecule sensitivity as compared to the conventional V-TFET device for neutral bio-molecules having dielectric constant of k = 7 and at Vgs = 0.9 V. Moreover, the transit time using the HJ-ESE-VTEFT is 50 % lower as compared to the C-VTFET means the proposed device is 2 times higher sensing speed as compare to the C-VTFET.
Design and estimation of GaAsSb/InGaAs hetero-junction double-dual gate vertical tunnel FET (HJ-VTFET) biosensor
Shailendra Singh, Jeetendra Singh
Journal of Materials Science Materials in Electronics, 2024
Advancement of Neuromorphic Computing Systems with Memristors
Jeetendra Singh, Shailendra Singh, Balwant Raj, Vikas Patel, Balwinder Raj
Integrated Devices for Artificial Intelligence and VLSI, 2024
A computing device is deemed rudimentary if its operational scope is confined to elementary high-school-level mathematical tasks. Conversely, a mechanism that incorporates components of biotic origin, like as DNA units, as opposed to conventional electrical elements, closely mirrors the intricacies of the human brain. The instantiation of a computation system that operates neurons and synapses in parallel, exhibiting high capacity and low power consumption, constitutes a neuromorphic computing system (NCS). Neurons communicate through the transmission of both chemical and electrical signals. A neural network is established through minuscule junctions, termed "synapses," where each neuron is intricately linked to others, facilitating signal propagation. Neuromorphic systems seamlessly integrate computing systems and memories, thereby mitigating the separation between them and overcoming the challenges associated with the "memory wall." This chapter provides an exhaustive perspective on neuromorphic computing, commencing with an examination of recent challenges in achieving effective computing systems capable of supporting diverse novel applications. Subsequently, device-level perspectives are scrutinized to enhance the efficacy of neuromorphic solutions. The comprehensive applications of neuromorphic computing are delineated to maximize exposure for research groups and the scientific community engaged in this field.
Highly sensitive N+ pocket doped vertical tunnel FET biosensor with wide range work function modulation gate electrodes
Girish Wadhwa, Jeetendra Singh, Anchal Thakur, Sheetal Bhandari
Materials Science and Engineering B, 2023
Design and Performance Analysis of Negative Capacitance Effect in the Charge Plasma-Based Junction-Less Vertical TFET Structure
Shailendra Singh, Jeetendra Singh
Nano, 2023
In this paper, a negative capacitance (NC) effect in series with normal oxide capacitance is first time introduced to design negative capacitance charge plasma-based junction less vertical TFET structure (NC-CP-JL-VTFET). The introduced negative capacitance enhances the overall gate capacitance and hence gate capacitive coupling and thus renders high current capabilities with reduced sub-threshold slope and threshold voltage. With the use of negative capacitance along with oxide capacitance, it has been seen that the same drain current is achieved at lower gate voltage as compared to without use of negative capacitance and since the voltage scaling is done considerably, the dynamic power dissipation in circuit application can be reduced significantly. To generate the negative capacitance during the device operation; ferroelectric material [Formula: see text](VDF-TrFE) poly(vinylidene fluoride-trifluoro ethylene) is used in stack with SiO2 gate oxide. Various performance parameters of the designed structure such as electron–hole concentration in the tunneling junction, electric field, surface potential, electron–hole quasi-Fermi variation, and drain current variation are investigated and compared with the results of without considering the ferroelectric material in the gate oxide. The variation of the ferroelectric thickness on the device performance is also investigated. The investigation exhibits significant improvement in the drain current and in the other parameters as well. These improvements are seen because of higher capacitive coupling and these effects are further responsible for more energy band bending which in turn govern high electron tunneling. Due to the existence of negative capacitance, the peak value of the electric field gets doubled while the surface potential increases 44% from the normal structure.
Integration of Particle Swarm Optimization (PSO) and Machine Learning to Improve Classification Accuracy During Antenna Design
Susheel Kumar Singh, Mukesh Kumar, Jeetendra Singh
Transactions on Electrical and Electronic Materials, 2023
Design and sensitivity estimation of linear graded work function gate electrode hetero junction vertical TFET biosensor
Jeetendra Singh, Girish Wadhwa, Balwinder Raj
Microsystem Technologies, 2023
Design and Integration of Vertical TFET and Memristor for Better Realization of Logical Functions
Jeetendra Singh, Shailendra Singh, Neha Paras
Silicon, 2023
Design and investigation of various memristor models for neuromorphic applications
Shailendra Singh, Raghav Dwivedi, Jeetendra Singh, Balwinder Raj
Nanoscale Memristor Device and Circuits Design, 2023
Modeling and Simulation Analysis Hetero Junction Doping Less Vertical TFET For Biomedical Application
Shailendra Singh, Jeetendra Singh, Arun Kumar Singh, Manoj Kumar Shukla
Silicon, 2022
Modeling Methods for Nanoscale Semiconductor Devices
Jeetendra Singh, Chhaya Verma
Silicon, 2022
Design and Self-Consistent Schrodinger-Poisson Model Simulation of Ultra-Thin Si-Channel Nanowire FET
Chhaya Verma, Jeetendra Singh
Silicon, 2022
Design and Performance Analysis of Ultrathin Nanowire FET Ammonia Gas Sensor
Chhaya Verma, Jeetendra Singh, Santosh Kumar Tripathi, Rajeev Kumar
Silicon, 2022
Design and Parametric Analysis of GaN on Silicon High Electron Mobility Transistor for RF Performance Enhancement
Jeetendra Singh, Archana Verma, Vijay Kumar Tewari, Shailendra Singh
Silicon, 2022
Investigation of N + SiGe Gate Stacked V-TFET Based on Dopingless Charge Plasma for Gas Sensing Application
Shailendra Singh, Archana Verma, Jeetendra Singh, Girish Wadhwa
Silicon, 2022
Design and Investigation of SiGe Heterojunction Based Charge Plasma Vertical TFET for Biosensing Application
Shailendra Singh, Amit Kumar Singh Chauhan, Gaurish Joshi, Jeetendra Singh
Silicon, 2022
Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance
Jeetendra Singh, Debapriya Chakraborty, Naveen Kumar
Silicon, 2022
Negf method for design and simulation analysis of nanoscale mos devices
Chhaya Verma, Jeetendra Singh
Sub Micron Semiconductor Devices Design and Applications, 2022
Investigation of Inherent Capacitive Effects in Linear Memristor Model
Jeetendra Singh, Sanjeev Kumar Sharma, Balwinder Raj
Silicon, 2021
Novel Linear Graded Binary Metal Alloy Pα Q1-α Gate Electrode and Middle N+ Pocket Si0.5Ge0.5 Vertical TFET for High Performance
Jeetendra Singh, Girish Wadhawa
Silicon, 2021
Design and Investigation of Doped Triple Metal Double Gate Vertical TFET for Performance Enhancement
Girish Wadhwa, Jeetendra Singh, Balwider Raj
Silicon, 2021
Design and Investigation of Junctionless DGTFET for Biological Molecule Recognition
Girish Wadhwa, Priyanka Kamboj, Jeetendra Singh, Balwinder Raj
Transactions on Electrical and Electronic Materials, 2021
Implementation of Memristor Towards Better Hardware/Software Security Design
Jeetendra Singh
Transactions on Electrical and Electronic Materials, 2021
Memristor: A Novel Device for Better Hardware/Software Security
Chhaya Verma, Jeetendra Singh
Nanoelectronic Devices for Hardware and Software Security, 2021
Brace of nanowire FETs in the advancements and miniaturizations of recent integrated circuits design
Debapriya Chakraborty, Jeetendra Singh, Shashi Bala
Innovative Applications of Nanowires for Circuit Design, 2020
Design and simulation analysis of NWFET for digital application
Shashi Bala, Raj Kumar, Jeetendra Singh, Sanjeev Kumar Sharma
Innovative Applications of Nanowires for Circuit Design, 2020
Implementation of linearly modulated work function AσB1−σ gate electrode and Si0.55Ge0.45 N+ pocket doping for performance improvement in gate stack vertical-TFET
Girish Wadhwa, Jeetendra Singh
Applied Physics A Materials Science and Processing, 2020
Design and performance analysis of FD silicon on insulator MOSFET
Chhaya Verma, Jeetendra Singh, Girish Wadhwa
2020 IEEE Students Conference on Engineering and Systems Sces 2020, 2020
An accurate and generic window function for nonlinear memristor models
Jeetendra Singh, Balwinder Raj
Journal of Computational Electronics, 2019
Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy
Jeetendra Singh, Balwinder Raj
IEEE Transactions on Very Large Scale Integration VLSI Systems, 2019
Tunnel current model of asymmetric MIM structure levying various image forces to analyze the characteristics of filamentary memristor
Jeetendra Singh, Balwinder Raj
Applied Physics A Materials Science and Processing, 2019
Temperature dependent analytical modeling and simulations of nanoscale memristor
Jeetendra Singh, Balwinder Raj
Engineering Science and Technology an International Journal, 2018
Comparative analysis of memristor models and memories design
Jeetendra Singh, Balwinder Raj
Journal of Semiconductors, 2018
Modeling of mean barrier height levying various image forces of metal-insulator-metal structure to enhance the performance of conductive filament based memristor model
Jeetendra Singh, Balwinder Raj
IEEE Transactions on Nanotechnology, 2018

RECENT SCHOLAR PUBLICATIONS

Design and Image Encryption Implementation of High Performance and Resource-Efficient AES-128 Encryption Architecture
DB Thakor, J Singh, B Raj
2025 IEEE 19th International Conference on Industrial and Information … , 2026
2026
Citations: 1
Radiations Effects on Advanced Multi-gate 3D Devices and Materials
R Kumar, VB Sreenivasulu, J Singh, S Bala
Transactions on Electrical and Electronic Materials 26 (5), 641-659 , 2025
2025
Citations: 1
434P: Clinicopathological characteristics and aggressive behavior of SMARCA4-deficient undifferentiated thoracic tumors mimicking NSCLC: Data from a tertiary cancer center in India
N Patnaik, R Duggal, A Dua, J Singh, PS Mane, S Saxena, V Goel
Journal of Thoracic Oncology 20 (3), S251 , 2025
2025
Improvement in the sensing performance of SiGe pocket Si/Ge VTFET based biosensor using extended source electrode and nano-cavity length
J Singh, S Singh
Materials Science and Engineering: B 310, 117688 , 2024
2024
Citations: 4
Advancement of Neuromorphic Computing Systems with Memristors
J Singh, S Singh, B Raj, V Patel, B Raj
Integrated Devices for Artificial Intelligence and VLSI, 193-215 , 2024
2024
Citations: 1
Design and estimation of GaAsSb/InGaAs hetero-junction double-dual gate vertical tunnel FET (HJ-VTFET) biosensor
S Singh, J Singh
Journal of Materials Science: Materials in Electronics 35 (2), 126 , 2024
2024
Citations: 6
Design and investigation of various memristor models for neuromorphic applications
S Singh, R Dwivedi, J Singh, B Raj
Nanoscale Memristor Device and Circuits Design, 21-38 , 2024
2024
Design and investigation
S Singha, R Dwivedia, J Singh, B Raj
Nanoscale Memristor Device and Circuits Design, 21 , 2023
2023
Highly sensitive N+ pocket doped vertical tunnel FET biosensor with wide range work function modulation gate electrodes
G Wadhwa, J Singh, A Thakur, S Bhandari
Materials Science and Engineering: B 297, 116730 , 2023
2023
Citations: 24
Design and Performance Analysis of Negative Capacitance Effect in the Charge Plasma-Based Junction-Less Vertical TFET Structure
S Singh, J Singh
Nano 18 (08), 2350060 , 2023
2023
Citations: 3
Integration of particle swarm optimization (PSO) and machine learning to improve classification accuracy during antenna design
SK Singh, M Kumar, J Singh
Transactions on Electrical and Electronic Materials 24 (3), 258-266 , 2023
2023
Citations: 6
Design and sensitivity estimation of linear graded work function gate electrode hetero junction vertical TFET biosensor
J Singh, G Wadhwa, B Raj
Microsystem Technologies 29 (2), 279-287 , 2023
2023
Citations: 17
Design and integration of vertical TFET and memristor for better realization of logical functions
J Singh, S Singh, N Paras
Silicon 15 (2), 783-792 , 2023
2023
Citations: 13
Advanced circuits and systems for healthcare and security applications
B Raj, BB Gupta, J Singh
CRC Press , 2022
2022
Citations: 2
Role of high-performance VLSI in the advancement of healthcare systems
J Singh, B Raj, M Khan
Advanced Circuits and Systems for Healthcare and Security Applications, 147-160 , 2022
2022
Citations: 3
Design and Analysis of Charge Plasma-Based SiGe Vertical TFET for Biosensing Applications
S Singh, SK Bhalla, J Singh, S Gupta, B Raj, NK Yadav
Advanced Circuits and Systems for Healthcare and Security Applications, 1-18 , 2022
2022
Shailendra Singh and Sanjeev Kumar Bhalla
J Singh, S Gupta, B Raj
Advanced Circuits and Systems for Healthcare and Security Applications, 1 , 2022
2022
Modeling and simulation analysis hetero junction doping less vertical TFET for biomedical application
S Singh, J Singh, AK Singh, MK Shukla
Silicon 14 (13), 8001-8008 , 2022
2022
Citations: 4
Design and investigation of SiGe heterojunction based charge plasma vertical TFET for biosensing application
S Singh, AKS Chauhan, G Joshi, J Singh
Silicon 14 (11), 6193-6204 , 2022
2022
Citations: 17
Investigation of N+ SiGe gate stacked V-TFET based on Dopingless charge plasma for gas sensing application
S Singh, A Verma, J Singh, G Wadhwa
Silicon 14 (11), 6205-6218 , 2022
2022
Citations: 22

MOST CITED SCHOLAR PUBLICATIONS

Design and investigation of 7T2M-NVSRAM with enhanced stability and temperature impact on store/restore energy
J Singh, B Raj
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (6 … , 2019
2019
Citations: 195
Temperature dependent analytical modeling and simulations of nanoscale memristor
J Singh, B Raj
Engineering science and technology, an international journal 21 (5), 862-868 , 2018
2018
Citations: 167
An accurate and generic window function for nonlinear memristor models
J Singh, B Raj
Journal of Computational Electronics 18 (2), 640-647 , 2019
2019
Citations: 163
Comparative analysis of memristor models and memories design
J Singh, B Raj
Journal of Semiconductors 39 (7), 074006 , 2018
2018
Citations: 160
Modeling of mean barrier height levying various image forces of metal–insulator–metal structure to enhance the performance of conductive filament based memristor model
J Singh, B Raj
IEEE Transactions on Nanotechnology 17 (2), 268-275 , 2018
2018
Citations: 157
Tunnel current model of asymmetric MIM structure levying various image forces to analyze the characteristics of filamentary memristor
J Singh, B Raj
Applied Physics A 125 (3), 203 , 2019
2019
Citations: 132
Design and performance analysis of nano-scale memristor-based nonvolatile static random access memory
J Singh, B Raj, M Khosla
Sensor Letters 16 (10), 798-805 , 2018
2018
Citations: 127
Analysis of barrier layer thickness on performance of In1–x Ga x as based gate stack cylindrical gate nanowire MOSFET
SK Sharma, J Singh, B Raj, M Khosla
Journal of Nanoelectronics and Optoelectronics 13 (10), 1473-1477 , 2018
2018
Citations: 120
Design and investigation of junctionless DGTFET for biological molecule recognition
G Wadhwa, P Kamboj, J Singh, B Raj
Transactions on electrical and electronic materials 22 (3), 282-289 , 2021
2021
Citations: 116
Enhanced nonlinear memristor model encapsulating stochastic dopant drift
J Singh, B Raj
Journal of Nanoelectronics and Optoelectronics 14 (7), 958-963 , 2019
2019
Citations: 111
Design and investigation of doped triple metal double gate vertical TFET for performance enhancement
G Wadhwa, J Singh, B Raj
Silicon 13 (6), 1839-1849 , 2021
2021
Citations: 35
Influence of growing environment on growth, yield and chemical composition of strawberry (Fragaria× ananassa) fruits under open vs naturally ventilated polyhouse conditions
S Pandey, J Singh, SK Singh, IB Mourya
Indian Journal of Agriculture Science 85, 1540-1545 , 2015
2015
Citations: 33
Implementation of memristor towards better hardware/software security design
J Singh
Transactions on Electrical and Electronic Materials 22 (1), 10-22 , 2021
2021
Citations: 30
Population dynamics of Pink bollworm Pectinophora gossypiella (Saunders) in cotton crop
SK Verma, DR Singh, J Singh, S Singh, N Yadav
International Journal of Pure & Applied Bioscience 5 (2), 801-806 , 2017
2017
Citations: 25
Highly sensitive N+ pocket doped vertical tunnel FET biosensor with wide range work function modulation gate electrodes
G Wadhwa, J Singh, A Thakur, S Bhandari
Materials Science and Engineering: B 297, 116730 , 2023
2023
Citations: 24
Design and performance analysis of ultrathin nanowire FET ammonia gas sensor
C Verma, J Singh, SK Tripathi, R Kumar
Silicon 14 (11), 6321-6327 , 2022
2022
Citations: 23
Investigation of N+ SiGe gate stacked V-TFET based on Dopingless charge plasma for gas sensing application
S Singh, A Verma, J Singh, G Wadhwa
Silicon 14 (11), 6205-6218 , 2022
2022
Citations: 22
Implementation of linearly modulated work function A σ B 1−σ gate electrode and Si 0.55 Ge 0.45 N+ pocket doping for performance improvement in gate stack …
G Wadhwa, J Singh
Applied Physics A 126 (11), 877 , 2020
2020
Citations: 22
Investigation of inherent capacitive effects in linear memristor model
J Singh, SK Sharma, B Raj
Silicon 13 (10), 3423-3430 , 2021
2021
Citations: 21
Mamta Khosla analysis of barrier layer thickness on performance of In1-xGaxAs based gate stack cylindrical gate nanowire MOSFET
J Singh, S Sharma, B Raj
Journal of Nanoelectronics and Optoelectronics 13, 1473-1477 , 2018
2018
Citations: 20

Jeetendra Singh

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Scopus Publications

RECENT SCHOLAR PUBLICATIONS

MOST CITED SCHOLAR PUBLICATIONS