Optimization of Ripple Carry Adder using Quantum Computing N.Parvatham, Rithiga R, Ruzmina M, Arthi Archisha S Proceedings of 5th International Conference on Ubiquitous Computing and Intelligent Information Systems Icuis 2025, 2025 This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
Exploration of Inaccessible Fibrins in SEM of RBC using Fractal based Modified Segregation Scoring Approach Parvatham Vijay Proceedings of the 2024 International Conference on Emerging Techniques in Computational Intelligence Icetci 2024, 2024 Deep vein thrombosis (DVT) can be very serious because blood clots in veins can break loose, travel through our bloodstream and lodge in our lungs, blocking blood flow. Aim of this paper is to analyse the depth of blood coagulation and fibrin structure in veins using the proposed MF-DAS method. Using SEM for RBC blood coagulated specimens as the base image, both DVT -patients and normal people images were taken, and the MF-DAS images were obtained, exploring deeper fibrins unexplored by the original SEM images nor by their segmented counterparts, which clearly delineated the fibrins from the rest. The Box counting algorithm is used to find the slope of the SEM images. If the slope value is closer to dimension 2 are called as unaffected images. Or else, if there is more deviation, then the images are blood clot images. The proposed algorithm is used for finding the deep analysis of thrombosis images.
Detection and Categorization of Breast Cancer Using Machine Learning N Parvatham, P A Saye Sudharsana, E Lavanya, A Savithavani Proceedings of the 2024 10th International Conference on Communication and Signal Processing Iccsp 2024, 2024 Cancer that originates in the breast tissue is known as breast cancer. A breast lump, breast form changes, skin dimpling, fluid flowing from the nipple, a newly inverted nipple, or a red or scaly patch of skin can all be indicators of breast cancer. Yellow skin, shortness of breath, enlarged lymph nodes, and bone pain are possible symptoms in those whose disease has progressed far. The initial goal is to examine the different deep learning models for image classification of breast cancer histology. According to research, the majority of skilled medical professionals can identify cancer with 79% accuracy, however machine learning approaches can obtain a 91% right diagnosis. Delaying the growth of a tumor or breast cancer has long-term consequences and may even be fatal. Therefore, it is important to detect the tumor as soon as possible in order to stop its growth and stop it from spreading to other tissues. It is typically recommended to undergo a mammography procedure in order to detect and diagnose breast cancer early.
Automatic Design of various Reinforced Concrete Structures based on AutoCAD AutoLISP Dharani V P, Parvatham Vijay Proceedings of the International Symposium on Automation and Robotics in Construction, 2023 The objective of this paper is to develop different automatic designs for building construction using a new tool called AutoCAD AutoLISP.One-way slab, Reinforced Cement Concrete pipe, straight stairs spanning horizontally, Circular tank over the ground and a Square Column Footing.These are the designs developed using AutoLISP software.Five Library functions are developed to get the 3D model for these designs.After getting the input parameters from the user, the required design structure will be generated automatically.The advantage of this tool is that since the library is created, the import of drawings in the structural analysis will be easy; it will shorten the design period compared to other software.Developing all types of slabs, stairs and tanks using this software will be more beneficial to improve the design efficiency and quality.
Light-Weight Present Block Cipher Model for IoT Security on FPGA R. Bharathi, N. Parvatham Intelligent Automation and Soft Computing, 2022 The Internet of Things (IoT) plays an essential role in connecting a small number of billion devices with people for diverse applications. The security and privacy with authentication are challenging work for IoT devices. A lightweight block cipher is designed and modeled with IoT security for real-time scenarios to overcome the above challenges. The light-weight PRESENT module with the integration of encryption (E)-decryption (D) is modeled and implemented on FPGA. The PRESENT module has 64-bit data input with 80/128/256-bit symmetric keys for IoT security. The PRESENT module performs16/32/64 round operations for state register and key updation. The design mainly uses Substitution-permutation (SP) network for state updation. The permutation layer is used to create more diffusion and confusion in the state for unauthorized access. The results and analysis of the PRESENT-80/128/256 are designed using VerilogHDL with Xilinx Environment and implemented on Artix-7 FPGA. The PRESENT-80/128/256 module is compared with similar recent works with performance improvements. Similarly, the proposed work is compared with different light-weight algorithms with improvements for better security in IoT devices. The proposed PRESENT-256 module with 64-rounds on Artix-7 FPGA utilizes less than 2% Chip area (Slices and LUTs), works at 412.4 MHz frequency, and consumes 192 mW total power and 0.58 Mbps/slice of hardware efficiency.
LEA-SIoT: Hardware architecture of lightweight encryption algorithm for secure IoT on FPGA platform International Journal of Advanced Computer Science and Applications, 2020
A novel development of wireless mesh protocol data transmission framework for internet based energy conservation Acta Technica CSAV Ceskoslovensk Akademie Ved, 2018
A novel development of wireless mesh protocol data transmission framework for internet-based energy conservation Acta Technica CSAV Ceskoslovensk Akademie Ved, 2018
Design of Finite Impulse Response Filter for 1-D Discrete Wavelet Transform using Parallel and Pipelining Approach P Goutham Proceedings of International Conference on Frontiers in Engineering, Applied … , 2018 2018.0
Design of Finite Impulse Response Filter for 1-D Discrete Wavelet Transform using Parallel and Pipelining Approach GC Parvatham Vijay Proceedings of International Conference on Frontiers in Engineering, Applied … , 2018 2018.0
A novel development of wireless mesh protocol data transmission framework for internet based energy conservation P Vijayasaro.V Nithyanandam.S Acta Technica 63, 1-8 , 2018 2018.0
An IOT Based Real Time Implementation Solution for Energy Crisis Using Bluetooth P Vijayasaro.V Nithyanandam.S International Journal of Pure and Applied Mathematics 117 (20), 1-8 , 2017 2017.0
New Design for FIR Filter with Optimization of Speed and Power Using ASIC DRP Parvatham vijay Asian Journal of Information technology 15 (6), 1090-1097 , 2016 2016.0
Field Programmable Gate Arrays Implementation of Multiplier Free Architecture for Image Compression P Vijay, S Gopalakrishnan Advanced Science Letters 20 (10-11), 2050-2054 , 2014 2014.0
Application Specific Integrated Circuit Implementation of Multiplier Free Modified Flipping Architecture for Image Compression P Vijay, S Gopalakrishnan Advanced Science Letters 20 (10-11), 2055-2059 , 2014 2014.0
A novel approach for and efficient implementation of 2 Level 2D DWT using ASIC and FPGA P Vijay, S Gopalakrishnan 2013 1st International Conference on Emerging Trends and Applications in … , 2013 2013.0 Citations: 3
Implementation of one level 2D DWT using multiplier less modified flipping architecture S Gopalakrishnan 2013 7th Asia Modelling Symposium, 137-142 , 2013 2013.0 Citations: 1
SEM Medical image processing using VLSI B R ICCIP-2019,17-18 MAY 2019,Mumbai , 0
MOST CITED SCHOLAR PUBLICATIONS
A novel approach for and efficient implementation of 2 Level 2D DWT using ASIC and FPGA P Vijay, S Gopalakrishnan 2013 1st International Conference on Emerging Trends and Applications in … , 2013 2013.0 Citations: 3
Implementation of one level 2D DWT using multiplier less modified flipping architecture S Gopalakrishnan 2013 7th Asia Modelling Symposium, 137-142 , 2013 2013.0 Citations: 1
Design of Finite Impulse Response Filter for 1-D Discrete Wavelet Transform using Parallel and Pipelining Approach P Goutham Proceedings of International Conference on Frontiers in Engineering, Applied … , 2018 2018.0
Design of Finite Impulse Response Filter for 1-D Discrete Wavelet Transform using Parallel and Pipelining Approach GC Parvatham Vijay Proceedings of International Conference on Frontiers in Engineering, Applied … , 2018 2018.0
A novel development of wireless mesh protocol data transmission framework for internet based energy conservation P Vijayasaro.V Nithyanandam.S Acta Technica 63, 1-8 , 2018 2018.0
An IOT Based Real Time Implementation Solution for Energy Crisis Using Bluetooth P Vijayasaro.V Nithyanandam.S International Journal of Pure and Applied Mathematics 117 (20), 1-8 , 2017 2017.0
New Design for FIR Filter with Optimization of Speed and Power Using ASIC DRP Parvatham vijay Asian Journal of Information technology 15 (6), 1090-1097 , 2016 2016.0
Field Programmable Gate Arrays Implementation of Multiplier Free Architecture for Image Compression P Vijay, S Gopalakrishnan Advanced Science Letters 20 (10-11), 2050-2054 , 2014 2014.0
Application Specific Integrated Circuit Implementation of Multiplier Free Modified Flipping Architecture for Image Compression P Vijay, S Gopalakrishnan Advanced Science Letters 20 (10-11), 2055-2059 , 2014 2014.0
SEM Medical image processing using VLSI B R ICCIP-2019,17-18 MAY 2019,Mumbai , 0
