Dr.KALAMANI C

@tnce.in

Professor and ECE
Tamilnadu College of Engineering



              

https://researchid.co/kalamec18

EDUCATION

B.E,M.Tech,P.hD

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering, Control and Systems Engineering, Industrial and Manufacturing Engineering, Architecture

12

Scopus Publications

36

Scholar Citations

3

Scholar h-index

1

Scholar i10-index

Scopus Publications

  • Design of encoder and decoder using reversible logic gates
    C. Kalamani, R. Murugasami, S. Usha, and S. Saravanakumar

    Elsevier BV

  • An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm
    C. Kalamani, S. Lekashri, A.N. Duraivel, and T. Selvin Retna Raj

    Informa UK Limited
    ABSTRACT The digital filters play a significant role in the field of digital signal processing (DSP). The finite impulse response (FIR) filter is an attractive choice because of the ease of design and good stability. The digital filters have a wide variety of applications such as signal processing, control systems, telecommunication, etc. They are better than the analogue filters due to their performance. In recent times, software radios have achieved attention owing to requirements for integrated and reconfigurable communication systems. Hence, reconfigurations have emerged as a significant problem in the designs of FIRs. To match the frequencies of DSP applications, higher-order FIRs are required. If length of filters rises, addition and multiplication operations also increase. This paper proposes an efficient hardware design of RFIR that employs modified bacterial foraging optimizations (MBFOs) and common sub-expression eliminations (CSEs) in its executions. MBFOs output restricted counts of filter coefficients with sums of signed-power-of-two (SPT) terms while maintaining the quality of filtered responses. On obtaining coefficients, eliminations are executed by CSEs where hardware complexities are determined in terms of adders. Model sim software validated RFIRs using the Verilog code. The proposed design of RFIRs was compared with existing designs in terms of power usages, frequencies and areas.

  • Photographic Attendance Tracking System Online (PATSO)
    Rajadurai S, Dhinesh N, Karthikeyan S, and Kalamani C

    IEEE
    Attendance tracking is critical to monitoring student or employee attendance in academic and organizational settings. With the rise of online education and remote work, traditional attendance tracking methods are becoming less effective. This paper proposes a web application for an image- based online attendance tracking system (PATSO) that utilizes machine learning algorithm SVM for classification and face recognition technique to identify and track attendance. The system gets a group or an individual image of students from the user and compares them to a pre-stored database of images to verify attendance. The proposed method is convenient, and accurate, and eliminates the need for manual attendance tracking not only in online mode but also in offline modes. The system's effectiveness was evaluated through a series of experiments, which showed a high accuracy rate of over 90%.

  • The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals
    Kalamani C., Kamatchi S., Sasikala S., and Murali L.

    Informa UK Limited

  • Design of Power Delay Efficient Wallace Muliplier
    Kalamani. C, Dharani, Vanjipriya, and Ishwarya Niranjana. M

    IEEE
    In applications involving image processing, multipliers are crucial. Area, potency, and delay analysis of the circuit are a few of the different metrics used to describe the performance of digital analysis. The 4-bit AXB is multiplied by a 4X4 Wallace tree resulting in the formation of a fractional creation, which causes an incrimination in latency. The delay is further decremented by inserting a 4-2 compressor in the fractional creation generation phase and it is used to implement 8bit Wallace multiplier to reduce delay. The simulated result shows a decrease in power and delay.

  • Design and Simulation of Microstrip Patch Antenna Using Circular Structure
    Kalamani. C, Abiramasundari. S, Dhanasekar. J, and Ishwarya Niranjana. M

    IEEE
    Microstrip patch antennas are castoff in various applications. It uses resonant cavity for its radiation. The various antennas are designed in the past. The proposed antennas are designed with single patch, array with rectangular structure and array antenna with circular structure using ADS software. Both single and array with rectangular are operating in three band of frequency at 4.5,5. 7and 7.6 Giga hertz. The performances of these antennas are increased by inserting λ/4 between transmission line and patch. The performances improve further by making circular structure. This circular structure is operating in the 5.8 Gigahertz and used in RFID and WLAN application.

  • Design of Power and Delay Efficient Fault Tolerant Adder
    Kalamani C, Vivek Karthick Perumal, M. Vivek Kumar, and J. Muralidharan

    IEEE
    A power, delay efficient error acquiescent adder is proposed. In recent VLSI expertise, the manifestation of all categories of faults has developed foreseeable. By embracing an emergent perception in VLSI strategy, fault-tolerant adder (FTA) is suggested. The FTA is talented to comfort the harsh constraint on exactitude, and at the identical period accomplish marvelous enhancements in together the power ingestion and speediness enactment. For any transportable uses anywhere the power ingestion and speed are the utmost significant limit, one must diminish the power feeding and upsurge the speed as ample as probable. In this technique certain amendments are suggested to predictable adders to significantly decrease its power feeding. The amendments to the conservative building comprise the elimination of carry generation from LSB to MSB. With this the adder works at high speed with low power consumption.

  • IoT based Smart Intravenous Fluids (IV) Drip Monitoring and Reverse Blood Flow Prevention System
    Vivek Kumar M, Ram Sundar. G, Manoharan. K, Kalamani. C, and Soumiya. S

    IEEE
    The most important prerequisite for providing advanced patient care in hospitals is hydration and electrolyte assessment and management. Electrolyte levels are manually checked in almost all hospitals. The patient's mortality could result from an incorrect bottle replacement. When the nurse failed to notice the notification or forget to replace the bottle once it gets emptied, there will be a high risk of reverse flow of blood. When the air gets locked up or the bottle gets emptier, it may lead to death of the patient. The proposed system monitors the entire process automatically. The setup also intimates the user through alert messages and notification at times. A warning popup notification is sent to the in charge/nurse and the caregivers based on the electrolyte levels with a unique key (room id & patient id). If they failed to notice the message and replace it, the smart tuning mechanism will block the fluid path and eliminates the reverse blood flow and the whole process stops automatically. Hence, there will not be any reverse blood flow or air bubble forming, which leads to death.

  • Automatic Head Gesture Controlled Robot
    Kalamani C, Pradeesh Kumar S, Kowsalya V, and Vinith Rahul M

    IEEE
    In this paper, Head Gestures has been defined as the mode of conversation while interacting with the robot. The head gesture robotic is really helpful to limit human efforts and lift out fantastic results. Head gesture robot makes use of the easy module like Arduino, gyroscope and RF Module, which is discovered to be positive than different Wi-Fi module. The gyroscope relies upon the gestures of the head. Through gyroscope, a passage of data signal is obtained and it is processed with assist of aruino microcontroller. In three-axis gyroscope, one axis will govern the pace in ahead or backward course and different axis will alter the spinning mechanism. The microcontroller provided instructions to the robot to travel in the prefered direction. The primary working precept for the robotic is passage of the records indicators of gyroscope readings to the arduino board equipped on the bot. The usage of the eye blink sensor in the transmitter helps to automatic turn on/off the robot. The software compiled in that arduino runs in accordance to that value, which make the bot characteristics accordingly.

  • Hybrid encoding for test data compression
    C. Kalamani, M. Mayilsamy, V. Rukkumani, K. Srinivasan, R. Mohan Kumar, and K. Paramasivam

    Elsevier BV


  • A mixed selected selective huffman coding and run length coding techniques for test data compression


RECENT SCHOLAR PUBLICATIONS

  • Design of encoder and decoder using reversible logic gates
    C Kalamani, R Murugasami, S Usha, S Saravanakumar
    Measurement: Sensors 31, 100989 2024

  • An efficient reconfigurable FIR filter design with coefficient optimization using a modified bacterial foraging optimization algorithm
    C Kalamani, S Lekashri, AN Duraivel, T Selvin Retna Raj
    Automatika 65 (1), 290-303 2024

  • The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals
    C Kalamani, S Kamatchi, S Sasikala, L Murali
    Automatika 64 (4), 772-782 2023

  • ASIC Flash Analog to Digital Convertor Using Operational Amplifier
    RPV C.Kalamani , Ram Karthik Kumar K., Kalai Selvi B.
    Tuijin Jishu\journal of Propulsion Technology 44 (6), 2437-2444 2023

  • Design and Simulation of Microstrip Patch Antenna Using Circular Structure
    Kalamani.C, Abiramasundari.S,Dhanasekar.j
    2023 9th International Conference on Advanced Computing and Communication 2023

  • Design of Power Delay Efficient Wallace Muliplier
    C Kalamani., Dharani, Vanjipriya, I Niranjana. M
    2023 9th International Conference on Advanced Computing and Communication 2023

  • IoT based Smart Intravenous Fluids (IV) Drip Monitoring and Reverse Blood Flow Prevention System
    V Kumar M, R Sundar. G, M K, K C, S S
    IEEE-2023 International Conference on Intelligent Data Communication 2023

  • Design of Power and Delay Efficient Fault Tolerant Adder
    C Kalamani, VK Perumal, MV Kumar, J Muralidharan
    2023 Third International Conference on Artificial Intelligence and Smart 2023

  • Design Of Adiabatic Circuits With Reversible Logic Based Full Adder And Multiplier In Current-Mode Logic Circuits For Efficient Power Dissipation
    C Kalamani, VS Nishok, A Asha, S Saravanakumar
    Optik, 170438 2022

  • ACCIDENT PREVENTION IN HILLY AREAS BY ALERT SYSTEM
    C Kalamani
    JOURNAL OF ENGINEERING, COMPUTING & ARCHITECTURE 12 (6), 190-197 2022

  • HAND GESTURE CONTROLLED CAR
    Dr.Kalamani C, Saamsundar K V , Mithun Adthiya P V
    JOURNAL OF ENGINEERING, COMPUTING & ARCHITECTURE 12 (6), 112-120 2022

  • Automatic Head Gesture Controlled Robot
    K C, P Kumar S, K V, V Rahul M
    IEEE-2022 International Conference on Communication, Computing and Internet 2022

  • IMPLEMENTATION OF KEYLESS DOORLOCK SYSTEM USING RASPERRY PI AND MOBILE APPLICATION
    Kalamani C, Shafiudeen M, Lakshmi Prabha V, Uva Priya V.G
    Vidyabharati International Interdisciplinary Research Journal ISSN: 2319 2021

  • Design and Development of Human Safety Detection Using GPS, GSM and RFID Technology
    Dr.Kalamani C, Athi Lakshmi G, Akshaya S
    Contemporary researCh in engineering and management 2, 31-44 2021

  • Design of Efficient R-Peak Detector for Electrocardiogram Signal
    Dr. C. Kalamani, N. Pavithra, S. Shanmathee
    AdvAncements in engineering and management 9, 111-127 2021

  • LOW RADIATION WEARABLE MICROSTRIP ANTENNAS FOR EMBEDDED SKIN PATCH APPLICATIONS
    P P., R Yathiraju, S E., A K. A., K S., S R., R M., R C., ...
    AU Patent 2,020,102,000 2020

  • Hybrid encoding for test data compression
    C Kalamani, M Mayilsamy, V Rukkumani, K Srinivasan, RM Kumar, ...
    Microprocessors and Microsystems 77, 103169 2020

  • Secured Mutual Authentication Protocol for Radio Frequency Identification Systems
    C Kalamani, S Sowmiya, S Dheivambigai, GH Sudhan
    International Journal of Electrical and Computer Engineering 14 (5), 138-143 2020

  • Design of Differential LNA and Double Balanced Mixer using 180 nm CMOS Technology
    C Kalamani
    Microprocessors and Microsystems 71 (1), - 2019

  • Implementation of low noise and mixer for CMOS Receiver Front
    KKK C.Kalamani V.Abishakkarthick,S.Anitha
    International Conference on Interdisciplinary Research innovations in 2018

MOST CITED SCHOLAR PUBLICATIONS

  • Design of Differential LNA and Double Balanced Mixer using 180 nm CMOS Technology
    C Kalamani
    Microprocessors and Microsystems 71 (1), - 2019
    Citations: 16

  • Design and Implementation of 4 Bit Multiplier Using Fault Tolerant Hybrid Full Adder
    C Kalamani, VA Karthick, S Anitha, KK Kumar
    International Journal of Electrical, Electronic and Communication Sciences 2017
    Citations: 6

  • A combined compatible block coding and run length coding techniques for test data compression
    C Kalamani, K Paramasivam
    World Appl. Sci. J. 32 (11), 2229-2233 2014
    Citations: 3

  • Design Of Adiabatic Circuits With Reversible Logic Based Full Adder And Multiplier In Current-Mode Logic Circuits For Efficient Power Dissipation
    C Kalamani, VS Nishok, A Asha, S Saravanakumar
    Optik, 170438 2022
    Citations: 2

  • Hybrid encoding for test data compression
    C Kalamani, M Mayilsamy, V Rukkumani, K Srinivasan, RM Kumar, ...
    Microprocessors and Microsystems 77, 103169 2020
    Citations: 2

  • VHDL based turbo encoder and decoder using cadence’
    MCK A.Amutha,G.Dharaniraja, R.Maheswari
    International Conference on recent trends in engineering and Technology. 2016
    Citations: 2

  • Survey of Low Power Testing Using Compression Techniques
    C Kalamani, DK Paramasivam
    International Journal of Electronics & Communication Technology 4 (4), 13-18 2013
    Citations: 2

  • The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals
    C Kalamani, S Kamatchi, S Sasikala, L Murali
    Automatika 64 (4), 772-782 2023
    Citations: 1

  • A Modified Run Length Coding Technique for Test Data Compression Based on Multi-Level Selective Huffman Coding
    C Kalamani
    International Journal of Electronics and Communication Engineering 11 (1 2017
    Citations: 1

  • Test Data Compression using a hybrid of bitmask dictionary and 2n Pattern Runlength Coding Methods
    C Kalamani, K Paramasivam
    World Academy of Science, Engineering and Technology 9 (3), 1289-1294 2015
    Citations: 1