Dr Swapnadip De is working as Associate Professor in ECE department of Meghnad Saha Institute of Technology since December 12, 2002. He completed his PhD in Engg. from Jadavpur University in June 2013. Prior to that he did M.Tech in VLSI and Microelectronics from JU, B.Tech in Radio physics and Electronics from CU and B.Sc in Physics Hons. from is currently the Officer In-Charge of MAKAUT examinations of MSIT since June 2024. He is currently the Branch Counselor of IEEE MSIT Student Branch for the past 3 years. He has authored 34 Journals, 16 books/book chapters published 3 patents and 17 Conference papers.
EDUCATION
PhD(Engg.) from JU, M. Tech from JU, B. Tech from CU B. Sc in Physics Honours from CU
RESEARCH, TEACHING, or OTHER INTERESTS
Engineering, Modeling and Simulation, Electrical and Electronic Engineering, Multidisciplinary
22
Scopus Publications
787
Scholar Citations
13
Scholar h-index
16
Scholar i10-index
Scopus Publications
Sentiment Analysis of Bengali-English-Hindi Code-Mixed Text: A Comparative Evaluation of Classical and Transformer Based Models Debarati Chakrabarti, Papiya Debnath, Swapnadip De, Manash Chanda 2026 International Conference on Signal Analysis for Smart Systems Signass 2026, 2026 This study investigates sentiment analysis on code-mixed Bengali, English, and Hindi text, evaluating both transformer-based architectures and traditional machinelearning models. Experimental results show that multilingual transformers significantly outperform classical approaches in capturing complex multilingual and contextual patterns. The mBERT model achieved the highest weighted F1 score of 0.75, followed by XLM RoBERTa with 0.73, highlighting the effectiveness of fine-tuned multilingual Pre trained Language Models (PLMs) for code-mixed data. Among classical baselines, Support Vector Machine performed best with an F1 score of 0.677, demonstrating that TF IDF and n-gram features remain competitive for mixed-language tasks. These findings emphasize that multilingual pre training and cross lingual alignment are essential for robust sentiment analysis in code-mixed environments.
Parameter modeling of linearly doped double gate MOSFET with high-k dielectrics Srijan Das, Anirban Choudhury, Soham Ghosh, Sudeshna Sarkar, Manash Chanda, Swapnadip De Proceedings of 2nd International Conference on 2017 Devices for Integrated Circuit Devic 2017, 2017 In this paper an analytical expression of surface potential, threshold voltage and drain current for Single halo Dual Material Double Gate, Double Halo Dual Material Double Gate and Double Halo Triple Material Double Gate MOSFETs are formulated by applying Gauss' law to a rectangular box in the channel region, covering the total depth of depletion region. The characteristic parameters are formulated for sub threshold regime. The uniqueness of this model lies in the fact that high-k dielectrics are used instead of Silicon dioxide. It is seen that the Triple Material Double Gate structure suppresses the short channel effects most effectively when compared to the other two. The doping profile concentrations of the two halos were considered linear with peak doping concentration at the two ends. The model results obtained by varying different parameters are compared with results obtained from the two-dimensional device simulator DESSIS. It is found that the model results tally quite effectively with those from DESSIS. So the proposed models are suitable for reducing the short channel effects and can be effectively used for devices operating in the sub-threshold region.
Adiabatic implementation of reversible architecture Anirban Chowdhury, Sandipta Mal, Shruti Goswami, Akash Mondal, Swapnadip De, Manash Chanda Proceedings of 2nd International Conference on 2017 Devices for Integrated Circuit Devic 2017, 2017 Reversible logic has gained significant attention in ultra-low power computing. Adiabatic implementation of reversible gate, i.e., TOFFOLI gate has been analyzed in depth in this paper. Energy efficient single sinusoidal source has ensured the correct operation in the proposed reversible adiabatic architectures. Single sinusoidal source minimizes the clocking overhead and also ensures minimal control overhead and higher energy efficiency. Power dissipation issue is addressed in depth here. Extensive simulations show that adiabatic reversible gates consume very less power compared to the conventional static CMOS architectures. Such an approach is efficacious for the design of ultra-low power VLSI circuits where speed is not a pivotal issue, like Internet of Things (IoT), sensor node designs and portable applications.
Basic semiconductor and metal-oxide-semiconductor (MOS) physics Technology Computer Aided Design Simulation for VLSI Mosfet, 2016
Low power VLSI design: Fundamentals Low Power VLSI Design Fundamentals, 2016
Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application Manash Chanda, Swapnadip De, Chandan Kumar Sarkar Journal of Circuits Systems and Computers, 2015 This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure.
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application Manash Chanda, Sankalp Jain, Swapnadip De, Chandan Kumar Sarkar IEEE Transactions on Very Large Scale Integration VLSI Systems, 2015 Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow-power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on subthreshold adiabatic logic-based 4-bit CLA has also been addressed separately. Postlayout simulations show that subthreshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.
Quasi-Fermi potential based analytical sub threshold drain current and transconductance model for practical DHDMG n-Mosfet International Journal of Applied Engineering Research, 2012
Application of Gaussian profile based DHDMG n-MOSFETs on deep submicron microelectronic circuits International Journal of Applied Engineering Research, 2012
Sentiment Analysis of Bengali-English-Hindi Code-Mixed Text: A Comparative Evaluation of Classical and Transformer Based Models D Chakrabarti, P Debnath, S De, M Chanda 2026 International Conference on Signal Analysis for Smart Systems (SIGNASS … , 2026 2026
Smart Voting Machine Using Rfid, Fingerprint And Password Security DSD Shristi Das, Saikat Biswas, Oyitijhya Das, Ankit Ghosh IJRAR - International Journal of Research and Analytical Reviews (IJRAR), E … , 2025 2025
Review of modelling of surface potential for channel and gate engineered MOSFETs in subthreshold regime DS Swapnadip De, Debasmita Ghosh IJRAR - International Journal of Research and Analytical Reviews (IJRAR), E … , 2024 2024
Artificial Intelligence based system for prediction and prevention of kidney disease using machine learning algorithms PJR Dr. Manash Chanda, Prof. Indrajit Das, Dr. Papiya Debnath, Dr. Swapnadip ... IN Patent App. 202,331,057,524 , 2024 2024
Review of Characteristic parameters for non-conventional Double Gate MOSFETs SS Swapnadip De, S Das, A Choudhary IJRAR - International Journal of Research and Analytical Reviews (IJRAR), E … , 2024 2024
Modelling of basic parameters for non-conventional MOSFETs S De Lambert Academic Publishing, Dudweiler Landstraße 9966123, Saarbrücken … , 2023 2023
AN INTELLIGENT MACHINE LEARNING BASED HEALTHCARE SYSTEM FOR MEDICAL EMERGENCY PSG Dr. Manash Chanda, Dr. Papiya Debnath, Prof. Indrajit Das, Prof ... IN Patent App. 202,331,013,263 , 2023 2023
A review of surface potential of short channel MOSFETs in subthreshold regime SD Swapnadip De , Angsuman Sarkar IJSDR - International Journal of Scientific Development and Research (www … , 2023 2023
Study of subthreshold surface potential of MOSFETs PD Swapnadip De, Ishita Gupta LAP, UK , 2023 2023
Basic concepts of Visual Media SD Meghavi Trivedi LAP, UK , 2023 2023
Study of Automatic Door Lock system S De Lambert Academic Publishing, Dudweiler Landstraße 9966123, Saarbrücken … , 2023 2023
Review of non conventional MOSFETs S De Lambert Academic Publishing, Dudweiler Landstraße 9966123, Saarbrücken … , 2023 2023
Internet of Things based Gas Chromatography PAD Prof. Subhrapratim Nath, Dr. Manash Chanda, Dr. Papiya Debnath, Prof ... IN Patent App. 350721-001 , 2022 2022
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics S De Technology Computer Aided Design, 61-160 , 2018 2018 Citations: 4
Crystallography, Band Structure, and Density of S De Nanotechnology: Synthesis to Applications, 3 , 2017 2017
Nanotechnology: synthesis to applications S Roy, CK Ghosh, CK Sarkar CRC Press , 2017 2017 Citations: 48
Crystallography, Band Structure, and Density of States at Nanoscale S De, S Roy, CK Ghosh, CK Sarkar Nanotechnology, 33-49 , 2017 2017
Adiabatic implementation of reversible architecture A Chowdhury, S Mal, S Goswami, A Mondal, S De, M Chanda 2017 Devices for Integrated Circuit (DevIC), 205-210 , 2017 2017 Citations: 1
Parameter modeling of linearly doped double gate MOSFET with high-k dielectrics S Das, A Choudhury, S Ghosh, S Sarkar, M Chanda, S De 2017 Devices for Integrated Circuit (DevIC), 136-140 , 2017 2017 Citations: 4
MOST CITED SCHOLAR PUBLICATIONS
Effect of gate engineering in double-gate MOSFETs for analog/RF applications A Sarkar, A Kumar Das, S De, C Kumar Sarkar Microelectronics Journal,Impact factor:0.91 43 (11), 873-882 , 2012 2012 Citations: 223
Implementation of subthreshold adiabatic logic for ultralow-power application M Chanda, S Jain, S De, CK Sarkar IEEE Transactions on very large scale integration (VLSI) systems 23 (12 … , 2015 2015 Citations: 79
Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model A Sarkar, S De, A Dey, CK Sarkar Journal of Computational Electronics,Impact factor:1.02 11 (2), 182-195 , 2012 2012 Citations: 61
Nanotechnology: synthesis to applications S Roy, CK Ghosh, CK Sarkar CRC Press , 2017 2017 Citations: 48
Low power VLSI design: fundamentals A Sarkar, S De, M Chanda, CK Sarkar Walter de Gruyter GmbH & Co KG , 2016 2016 Citations: 37
1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model A Sarkar, S De, A Dey, CK Sarkar IET circuits, devices & systems,Impact factor:1.01 6 (1), 28-34 , 2012 2012 Citations: 32
A new analytical subthreshold model of SRG MOSFET with analogue performance investigation A Sarkar, S De, A Dey, CK Sarkar International Journal of Electronics,Impact factor:0.51 99 (2), 267-283 , 2012 2012 Citations: 30
VLSI design and EDA tools A Sarkar, S De, CK Sarkar Scitech , 2011 2011 Citations: 27
Modeling of characteristic parameters for nano-scale junctionless double gate MOSFET considering quantum mechanical effect M Chanda, S De, CK Sarkar Journal of Computational Electronics 14 (1), 262-269 , 2015 2015 Citations: 26
Novel charge plasma based dielectric modulated impact ionization MOSFET as a biosensor for label-free detection M Chanda, P Dey, S De, CK Sarkar Superlattices and Microstructures 86, 446-455 , 2015 2015 Citations: 22
Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs S De, A Sarkar, CK Sarkar International Journal of Electronics,Impact factor:0.51 98 (10), 1365-1381 , 2011 2011 Citations: 22
Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling A Sarkar, S De, CK Sarkar International Journal of Numerical Modelling: Electronic Networks, Devices … , 2013 2013 Citations: 20
Asymmetric halo and symmetric SHDMG & DHDMGn‐MOSFETs characteristic parameter modeling A Sarkar, S De, CK Sarkar IJNM 26 (1), 41-55 , 2013 2013 Citations: 12
Fringing capacitance based surface potential model for pocket DMG n-MOSFETS S De, A Sarkar, CK Sarkar Journal of Electron Devices 12, 704-712 , 2012 2012 Citations: 11
Modelling of characteristic parameters for asymmetric DHDMG MOSFET S De, A Sarkar, CK Sarkar WSEAS Transactions on Circuits and Systems 11, 371-380 , 2012 2012 Citations: 10
Effect of fringing field in modeling of subthreshold surface potential in Dual Material Gate (DMG) MOSFETS S De, A Sarkar, N Mohankumar, CK Sarkar 2008 International Conference on Electrical and Computer Engineering, 148-151 , 2008 2008 Citations: 9
Modeling of Subthreshold Surface Potential for Short Channel Double Gate Dual Material Double Halo MOSFET. D Das, S De, M Chanda, C Kumar Sarkar IUP Journal of Electrical & Electronics Engineering 7 (4) , 2014 2014 Citations: 5
Effect of fringing fields on subthreshold surface potential of channel engineered short channel MOSFETs A Sarkar, S De, M Nagarajan, CK Sarkar, S Baishya TENCON 2008-2008 IEEE Region 10 Conference, 1-6 , 2008 2008 Citations: 5
Basic Semiconductor and Metal-Oxide-Semiconductor (MOS) Physics S De Technology Computer Aided Design, 61-160 , 2018 2018 Citations: 4
