REKIB UDDIN AHMED

@ritchennai.org

Assistant Professor, Electronics and Communication Engineering
Rajalakshmi Institute of Technology, Chennai

REKIB UDDIN AHMED


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https://researchid.co/rekib123

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering
17

Scopus Publications

54

Scholar Citations

5

Scholar h-index

1

Scholar i10-index

Scopus Publications

  • Efficient and accurate modeling of double-gate MOSFETs: a computationally feasible approach for potential, subthreshold, and drain current characteristics
    Rekib Uddin Ahmed, Arun Tej Mallajosyula
    Physica Scripta, 2025
    The continuous advancement of semiconductor technology has been driven by the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) to smaller dimensions, but this scaling is limited in the nanoscale regime due to short-channel effects (SCE). To address this limitation, the double-gate (DG) MOSFET has been proposed. For the effective utilization of the DG MOSFET in future semiconductor applications, accurate and robust models depicting its characteristics are essential. These models include potential distribution, subthreshold current, and drain current, where accuracy, complexity, and computational efficiency are crucial. This paper presents a modeling approach that reduces complexity in potential distribution, speeds up subthreshold current computation, and enhances drain current accuracy. The potential distribution is modeled using the superposition method, achieving a computational complexity of O ( N ) , which is more efficient than the widely used Green’s function method. The subthreshold current is modeled numerically, achieving a faster computation time of 0.1202 s compared to existing methods. A curve-fitting approach is applied to model the drain current, improving accuracy in both the transfer and output characteristics across different temperatures. The model is further integrated with artificial neural networks, achieving high predictive performance. The proposed models are validated using an industry-standard device simulator and benchmarked against existing methods.
  • Power-efficient VLSI realization of decimal convolution algorithms for resource-constrained environments: a design perspective in CMOS and double-gate CMOS technology
    Rekib Uddin Ahmed, Harsh Raj Thakur, M. A. Seenivasan, Prabir Saha
    Microsystem Technologies, 2025
  • Biologically inspired tonic and bursting LIF neuron model for spiking neural network: a CMOS implementation
    M. A. Seenivasan, Adarsh V. Parekkattil, Rekib Uddin Ahmed, Prabir Saha
    Microsystem Technologies, 2025
  • Efficient Modulo Multiplier
    Indian Institute of Technology Bombay, Rekib U. Ahmed, Sheba D. Thabah, IBM Systems, Mridul Haque, Indian Institute of Science, Prabir Saha, National Institute of Technology Meghalaya
    Electronics, 2023
    The paper presents the methodology to compute modulo multiplication with the moduli set 2n, 2n−1, 2n+1. In addition to this, designs of the modulo multipliers, namely 2n, 2n−1, and 2n+1 (with n = 4, 8, and 16), have been proposed which are based on half adders, full adders, 4:3 compressor, 7:3 compressor, and the multi-column compressor namely 5,5:4. The gate level design of 4:3 compressor is carried out by solving the truth table using the K-map reduction. To verify the functionalities we have implemented the proposed modulo multipliers using VHDL coding in Xilinx 14.2 design suite. Simulation using Virtex-6 device has been performed to estimate delay, power consumption, and power-delay product (PDP). Moreover, the modulo multipliers are simulated in Cadence RC compiler using 0.18 µm technology to estimate the area. One of the major contributions to the arts of this work is in the partial product reduction stage which utilizes the multi-column 5,5:4 compressor to reduce power and area. The modulo 2n−1 multiplier of operand size 4-bit shows an improvement of 66.34% in terms of area over the best-reported paper. On the other hand, the modulo 2n+1 multiplier of operand size 4-bit shows an improvement of 58.59% terms of in area and the same of operand size 8-bit shows an improvement of 22.72% over the best-reported paper. The proposed algorithms of moduli multiplication are applicable to Booth multiplication of signed numbers.
  • Design and Implementation of Multi-operand 2n- 1, 2n, and 2n+ 1 Modulo Set Adder
    Prabir Saha, Rekib Uddin Ahmed, Sheba Diamond Thabah
    Lecture Notes in Electrical Engineering, 2022
  • Implementation Aspects of Multi-bit Adders Using UTBSOI Transistors
    Rekib Uddin Ahmed, Prabir Saha
    Smart Innovation Systems and Technologies, 2021
  • On The Implementation of Densely Packed Decimal Number System based Adder: Prospects and Challenges
    National Institute of Technology Meghalaya, Srikant Kumar Beura, Rekib Uddin Ahmed, National Institute of Technology Meghalaya, Bishnulatpam Pushpa Devi, National Institute of Technology Meghalaya, Prabir Saha, National Institute of Technology Meghalaya
    Electronics, 2021
    Decimal digit number computation, through bit compression methodology, offers space and time saving, which can be incurred by the Chen-Ho and Densely Packed Decimal (DPD) coding techniques. Such coding techniques have a property of bit compression, like, three decimal digits can be represented by 10 bits instead of 12 bits in binary coded decimal (BCD) format. The compression has been obtained through the elimination of the redundant 0’s from BCD representation. This manuscript reports the pros and cons of the techniques mentioned above. The logic level functionalities have been examined through MATLAB, whereas circuit simulation has been erified through Cadence Spectre. Performance parameters (such as delay, power consumption) have been evaluated through CMOS gpdk45 nm technology. Furthermore, the best design has been chosen from them, and the decimal adder design technique has been incorporated in this paper.
  • Sensitivity Analysis of the UTBSOI Transistor based Two-Stage Operational Amplifier
    Rekib Uddin Ahmed, Eklare Akshay Vijaykumar, Prabir Saha
    Electronics, 2020
    In the nanoscale domain, the MOSFETs are prone to various physical effects due to their shorter channel region known as short-channel effects (SCE). The researchers have proposed an advanced structure of MOSFET known as the ultrathinbody silicon-on-insulator (UTBSOI) to overcome the limitations of SCEs. The UTBSOI is a type of double-gate (DG) MOSFET having superior controllability of gates over the shorter channel region. Nowadays, the UTBSOI MOSFETs can be adopted in the circuit simulators through the use of a device model named BSIM-IMG. The BSIM-IMG has made it possible for the circuit designers to simulate any UTBSOI based analog blocks like operational amplifiers (opamp). The performance parameters of an opamp are very much sensitive to any perturbation in size (W/L) of the constituent MOSFETs, that may cause a drastic change in the output. In this paper, the sensitivity analysis procedure has been proposed for the CMOS and UTBSOI based two-stage opamps as the function of perturbation in W/L. In addition to this, an algorithm has also been presented to do the same. From the simulation results, it is observed that the sensitivity of the UTBSOI based opamp (UTBSOI-opamp) is larger than that of CMOS based opamp (CMOS-opamp).
  • Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs
    Rekib Uddin Ahmed, Prabir Saha
    Electronics, 2020
    Nowadays, the endlessly increasing demand for faster and complex integrated circuits (IC) has been fuelled by the scaling of metal-oxide-semiconductor field-effect-transistors (MOSFET) to smaller dimensions. The continued scaling of MOSFETs approaches its physical limits due to short-channel effects (SCE). Double-gate (DG) MOSFET is one of the promising alternatives as it offers better immunity towards SCEs and can be scaled to the shortest channel length. In future, ICs can be designed using DG-CMOS technology for which mathematical models depicting the electrical characteristics of the DG MOSFETs are foremost needed. In this paper, a review on n-type symmetric DG MOSFETs models has been presented based on the analyses of electrostatic potential distribution, threshold voltage, and drain-current models. Mathematical derivations of the device models are described elaborately, and numerical simulations are also carried out to validate the replicability of models.
  • Modeling of short p-channel symmetric double-gate MOSFET for low power circuit simulation
    Rekib Uddin Ahmed, Prabir Saha
    Periodica Polytechnica Electrical Engineering and Computer Science, 2020
    In the present era, down scaling of complementary metal-oxide-semiconductor (CMOS) technology has lead the metal-oxide-semiconductor field-effect-transistor's (MOSFET) sizes to nanometer regime which in turn experiencing difficulties due to the effect of physical and technological perspective. Double-gate (DG) MOSFET is considered as a promising device to reduce the shortcoming and shrink down towards nanometer domain. This paper proposes electrostatic potential distribution and drain current models for the lightly doped symmetrical p-channel DG MOSFET. The analytic solution of potential distribution is derived by solving the 2D Poisson's equation incorporated with hole density through the superposition method. The drain current model has been explored by incorporating physical effects like threshold-voltage roll-off, channel length modulation and surface roughness scattering. Functionality of the models has been calculated in MATLAB and the obtained results are verified and compared with state of the art literature.
  • Power and delay comparison of 7:3 compressor designs based on different architectures of XOR gate
    Rekib Uddin Ahmed, Prabir Saha
    Lecture Notes in Networks and Systems, 2020
  • Design of double-gate cmos based two-stage operational transconductance amplifier using the utbsoi transistors
    UPB Scientific Bulletin Series C Electrical Engineering and Computer Science, 2020
  • Implementation Topology of Full Adder Cells
    Rekib Uddin Ahmed, Prabir Saha
    Procedia Computer Science, 2019
  • Design of New Multi-Column 5,5:4 Compressor Circuit Based on Double-Gate UTBSOI Transistors
    Rekib Uddin Ahmed, Sheba Diamond Thabah, Prabir Saha
    Procedia Computer Science, 2019
  • Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology
    Rekib Uddin Ahmed, Eklare Akshay Vijaykumar, Prabir Saha
    Electronics, 2019
  • Fast and Area Efficient Implementation of RSA Algorithm
    Sheba Diamond Thabah, Mridupawan Sonowal, Rekib Uddin Ahmed, Prabir Saha
    Procedia Computer Science, 2019
  • Modeling of threshold voltage and subthreshold current for p-channel symmetric double-gate MOSFET in nanoscale regime
    Rekib Uddin Ahmed, Prabir Saha
    Proceedings 2017 IEEE International Symposium on Nanoelectronic and Information Systems Inis 2017, 2017

RECENT SCHOLAR PUBLICATIONS

  • Efficient and accurate modeling of double-gate MOSFETs: a computationally feasible approach for potential, subthreshold, and drain current characteristics
    RU Ahmed, AT Mallajosyula
    Physica Scripta 100 (8), 085414 , 2025
    2025
  • Biologically inspired tonic and bursting LIF neuron model for spiking neural network: a CMOS implementation
    MA Seenivasan, AV Parekkattil, RU Ahmed, P Saha
    Microsystem Technologies 31 (2), 475-489 , 2024
    2024
    Citations: 6
  • Power-efficient VLSI realization of decimal convolution algorithms for resource-constrained environments: a design perspective in CMOS and double-gate CMOS technology
    RU Ahmed, HR Thakur, MA Seenivasan, P Saha
    Microsystem Technologies 31 (2), 313-325 , 2024
    2024
    Citations: 5
  • Efficient Modulo Multiplier
    RU Ahmed, SD Thabah, M Haque, P Saha
    Electronics 27 (1), 18-24 , 2023
    2023
  • Design and Implementation of Multi-operand 2 , 2 , and 2 Modulo Set Adder
    P Saha, RU Ahmed, SD Thabah
    Advances in Communication, Devices and Networking: Proceedings of ICCDN 2020 … , 2021
    2021
    Citations: 1
  • Design and Analysis of Computational Circuits using Multi Gate Nanoscale Device
    RU Ahmed
    Shillong , 2021
    2021
  • On The Implementation of Densely Packed Decimal Number System based Adder: Prospects and Challenges
    SK Beura, RU Ahmed, BP Devi, P Saha
    Electronics 25 (1), 20-30 , 2021
    2021
  • Implementation Aspects of Multi-bit Adders Using UTBSOI Transistors
    RU Ahmed, P Saha
    Smart Trends in Computing and Communications: Proceedings of SmartCom 2020 … , 2020
    2020
    Citations: 1
  • Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs
    RU Ahmed, P Saha
    Electronics 24 (1), 17-34 , 2020
    2020
    Citations: 2
  • Power and delay comparison of 7: 3 compressor designs based on different architectures of XOR gate
    RU Ahmed, P Saha
    Inventive Communication and Computational Technologies: Proceedings of … , 2020
    2020
    Citations: 2
  • Sensitivity Analysis of the UTBSOI Transistor based Two-Stage Operational Amplifier
    RU Ahmed, EA Vijaykumar, P Saha
    Electronics 24 (2), 75-80 , 2020
    2020
  • Design of Double-Gate CMOS based Two-Stage Operational Transconductance Amplifier using the UTBSOI Transistors
    RU AHMED, EA VIJAYKUMAR, HS PONAKALA, MYV BALAJI, P SAHA
    UPB Scientific Bulletin, Series C: Electrical Engineerng and Computer … , 2020
    2020
    Citations: 6
  • Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation
    RU Ahmed, P Saha
    Periodica Polytechnica Electrical Engineering and Computer Science 64 (1 … , 2019
    2019
    Citations: 1
  • Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology
    RU Ahmed, EA Vijaykumar, P Saha
    Electronics 23 (2), 52-59 , 2019
    2019
    Citations: 7
  • Design of new multi-column 5, 5: 4 compressor circuit based on double-gate UTBSOI transistors
    RU Ahmed, SD Thabah, P Saha
    Procedia Computer Science 165, 532-540 , 2019
    2019
    Citations: 3
  • Fast and area efficient implementation of RSA algorithm
    SD Thabah, M Sonowal, RU Ahmed, P Saha
    Procedia Computer Science 165, 525-531 , 2019
    2019
    Citations: 12
  • Implementation topology of full adder cells
    RU Ahmed, P Saha
    Procedia Computer Science 165, 676-683 , 2019
    2019
    Citations: 5
  • Modeling of threshold voltage and subthreshold current for p-channel symmetric double-gate MOSFET in nanoscale regime
    RU Ahmed, P Saha
    2017 IEEE International Symposium on Nanoelectronic and Information Systems … , 2017
    2017
    Citations: 3
  • Modeling of Potential and Threshold Voltage in presence of Hot-Carriers for Short-Channel Double-Gate MOSFET
    RU Ahmed, RK Baruah
    Advanced Research in Electrical and Electronic Engineering 2 (11), 15-20 , 2015
    2015

MOST CITED SCHOLAR PUBLICATIONS

  • Fast and area efficient implementation of RSA algorithm
    SD Thabah, M Sonowal, RU Ahmed, P Saha
    Procedia Computer Science 165, 525-531 , 2019
    2019
    Citations: 12
  • Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology
    RU Ahmed, EA Vijaykumar, P Saha
    Electronics 23 (2), 52-59 , 2019
    2019
    Citations: 7
  • Biologically inspired tonic and bursting LIF neuron model for spiking neural network: a CMOS implementation
    MA Seenivasan, AV Parekkattil, RU Ahmed, P Saha
    Microsystem Technologies 31 (2), 475-489 , 2024
    2024
    Citations: 6
  • Design of Double-Gate CMOS based Two-Stage Operational Transconductance Amplifier using the UTBSOI Transistors
    RU AHMED, EA VIJAYKUMAR, HS PONAKALA, MYV BALAJI, P SAHA
    UPB Scientific Bulletin, Series C: Electrical Engineerng and Computer … , 2020
    2020
    Citations: 6
  • Power-efficient VLSI realization of decimal convolution algorithms for resource-constrained environments: a design perspective in CMOS and double-gate CMOS technology
    RU Ahmed, HR Thakur, MA Seenivasan, P Saha
    Microsystem Technologies 31 (2), 313-325 , 2024
    2024
    Citations: 5
  • Implementation topology of full adder cells
    RU Ahmed, P Saha
    Procedia Computer Science 165, 676-683 , 2019
    2019
    Citations: 5
  • Design of new multi-column 5, 5: 4 compressor circuit based on double-gate UTBSOI transistors
    RU Ahmed, SD Thabah, P Saha
    Procedia Computer Science 165, 532-540 , 2019
    2019
    Citations: 3
  • Modeling of threshold voltage and subthreshold current for p-channel symmetric double-gate MOSFET in nanoscale regime
    RU Ahmed, P Saha
    2017 IEEE International Symposium on Nanoelectronic and Information Systems … , 2017
    2017
    Citations: 3
  • Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs
    RU Ahmed, P Saha
    Electronics 24 (1), 17-34 , 2020
    2020
    Citations: 2
  • Power and delay comparison of 7: 3 compressor designs based on different architectures of XOR gate
    RU Ahmed, P Saha
    Inventive Communication and Computational Technologies: Proceedings of … , 2020
    2020
    Citations: 2
  • Design and Implementation of Multi-operand 2 , 2 , and 2 Modulo Set Adder
    P Saha, RU Ahmed, SD Thabah
    Advances in Communication, Devices and Networking: Proceedings of ICCDN 2020 … , 2021
    2021
    Citations: 1
  • Implementation Aspects of Multi-bit Adders Using UTBSOI Transistors
    RU Ahmed, P Saha
    Smart Trends in Computing and Communications: Proceedings of SmartCom 2020 … , 2020
    2020
    Citations: 1
  • Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation
    RU Ahmed, P Saha
    Periodica Polytechnica Electrical Engineering and Computer Science 64 (1 … , 2019
    2019
    Citations: 1
  • Efficient and accurate modeling of double-gate MOSFETs: a computationally feasible approach for potential, subthreshold, and drain current characteristics
    RU Ahmed, AT Mallajosyula
    Physica Scripta 100 (8), 085414 , 2025
    2025
  • Efficient Modulo Multiplier
    RU Ahmed, SD Thabah, M Haque, P Saha
    Electronics 27 (1), 18-24 , 2023
    2023
  • Design and Analysis of Computational Circuits using Multi Gate Nanoscale Device
    RU Ahmed
    Shillong , 2021
    2021
  • On The Implementation of Densely Packed Decimal Number System based Adder: Prospects and Challenges
    SK Beura, RU Ahmed, BP Devi, P Saha
    Electronics 25 (1), 20-30 , 2021
    2021
  • Sensitivity Analysis of the UTBSOI Transistor based Two-Stage Operational Amplifier
    RU Ahmed, EA Vijaykumar, P Saha
    Electronics 24 (2), 75-80 , 2020
    2020
  • Modeling of Potential and Threshold Voltage in presence of Hot-Carriers for Short-Channel Double-Gate MOSFET
    RU Ahmed, RK Baruah
    Advanced Research in Electrical and Electronic Engineering 2 (11), 15-20 , 2015
    2015