Dr. Subodh kumar Singhal
@juet.ac.in
Assistant Professor (SG), ECE
Jaypee University of Engineering and Technology, Guna
Received B.E. in Electronics and Communication engineering in 2004 from R.G.P.V, Bhopal, Received M.Tech in VLSI Design from ABV-IIITM, Gwalior in 2006 and Received Ph.D degree in the area of VLSI implementation of DSP Algorithms from JUET, Guna in 2017. In 2006 he was selected for SMDP project, sponsored by MHRD Government of India and joined as Research engineer in the Department of Electronics and Communication engineering, MANIT, Bhopal. In 2007 he joined Jaypee University of Engineering and Technology, Guna, Madhya Pradesh as a Assistance Professor. Currently he serves as the reviewers of various IEEE Transactions, Journal of Circuit, System and Signal Processing, Springer. He has member of various professional bodies like IEEE, IETE. His research interest includes various VLSI architectures design, ASIC and FPGA designs, Image processing. He has published nearly 6 technical papers.
EDUCATION
B.E., M.Tech., Ph.D.
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Signal Processing, Hardware and Architecture, Artificial Intelligence
Scopus Publications
Scopus Publications
Anuradha, Sujit Kumar Patel, and Subodh Kumar Singhal
Elsevier BV
Gaurav Saxena, Sarita Singh Bhadauria, and Subodh Kumar Singhal
IEEE
Haze removal techniques are widely used in various computer vision applications like object detection, tracking, target recognition, and video surveillance. Therefore, in this paper, the classification of different fog removal techniques is presented. Further, recent dehazing algorithms related to each category are analyzed for the restoration of atmospherically degraded images. However, the performance of the different algorithms is evaluated based on the most commonly used image quality assessment parameters. Hence, different comparison parameters utilized for the evaluation of the performance of the various dehazing algorithms are also discussed. Finally, the qualitative and quantitative comparison of the various state-of-art defogging algorithms and research scope for further improvement is discussed.
Subodh K. SINGHAL, Sujit K. PATEL, Anurag MAHAJAN, and Gaurav SAXENA
The Scientific and Technological Research Council of Turkey (TUBITAK-ULAKBIM) - DIGITAL COMMONS JOURNALS
Subodh Kumar Singhal, B. K. Mohanty, Sujit Kumar Patel, and Gaurav Saxena
World Scientific Pub Co Pte Lt
Parallel prefix adder (PPA) is the core component of diminished-1 modulo ([Formula: see text]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo ([Formula: see text]) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo ([Formula: see text]) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energy-delay-product (EDP) than the best of the existing modulo adder structure.
Sujit Kumar Patel and Subodh Kumar Singhal
Institution of Engineering and Technology (IET)
Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing RCA. Using this RCA design, the BTA structure is proposed. The synthesis result reveals that the proposed 32-operand BTA provides the saving of 22.5% in area–delay product and 28.7% in energy–delay product over the recent Wallace tree adder which is the best among available multi-operand adders. The authors have also applied the proposed BTA in the recent multiplier designs to evaluate its performance. The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA. Therefore, the proposed BTA design can be a better choice to develop the area, delay and energy efficient digital systems for signal and image processing applications.
Basant Kumar Mohanty and Subodh Kumar Singhal
Springer Science and Business Media LLC
Subodh Kumar Singhal and Basant Kumar Mohanty
World Scientific Pub Co Pte Lt
In this paper, we performed the complexity analysis of fixed-coefficient and variable-coefficient distributed arithmetic (DA)-based finite impulse response (FIR) filter structures to observe the effect of LUT decomposition on the area complexity of DA structure. The complexity analysis reveals that the area complexity of different units of DA FIR filter structure does not increase proportionately with the level of parallelism. An appropriate selection of LUT decomposition factor, and introducing higher level of parallelism in the computation could improve the area-delay efficiency of both fixed-coefficient and variable-coefficient DA-based FIR structures. Based on these findings, we have proposed bit-parallel block-based DA structures, for fixed-coefficient and variable-coefficient FIR. The proposed structures process one block of input samples and produce one block of outputs in every clock cycle. Theoretical estimate shows that the proposed fixed-coefficient structure, for block-size 8 and filter-length 32, involves eight times more ROM-LUT words, eight times more adders, two less registers, and offers eight times higher throughput-rate than the existing similar structure. For the same block-size and filter-length, the proposed variable-coefficient structure involves 7.2 times more adders, the same number of registers, eight times more MUXes, and offers eight times higher throughput than the best available similar structure. Synthesis result shows that the proposed fixed-coefficient structure for block-size 8 and filter-length 32 involve 47% less area delay product (ADP) and 42% less energy per sample (EPS) than the existing structure and offers nearly eight times higher throughput than others. For the same block-size and filter-length, the proposed structure for variable-coefficient FIR involves 71% less ADP and 65% less EPS than the similar existing structures.
Basant Kumar Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal, and M.N.S. Swamy
Elsevier BV
Basant Kumar Mohanty, Pramod Kumar Meher, and Subodh Kumar Singhal
IEEE
In this paper, we present three different structures, namely the transposition-free structure, the folded structure and the pipeline structure for 2-D discrete Hadamard transform (DHT). The transposition-free structure and pipeline structure produce one column of output during each clock cycle, while the folded structure requires two clock cycles for that. The folded structure uses one 1-D DHT module for both row and column processing, while the pipeline structure processes rows and columns concurrently using two separate 1-D DHT modules. Interestingly, the transposition-unit of the pipeline structure involves nearly the same number of registers as the folded structure, and offers twice the throughput of the other. The transposition-free structure is less area-time efficient than pipeline structure due to its relatively less efficient serial-output processors. ASIC synthesis result shows that the pipeline structure involves 47.4% less area-delay product (ADP) and 53.74% less energy per sample (EPS) than the folded structure, and involves slightly less ADP and consumes 31.67% less EPS than the transposition-free design.
Deepak Sharma, Subodh Kumar Singhal, and Ram Mehar Singh Dhariwal
IEEE
This paper presents a quasilumped microstrip structure highpass filter having a cutoff frequency 1.5 GHz. The quasilumped elements used for this design have their size smaller then the quarter of the guided wavelength at the operating frequency. The proposed designs is a three pole filter, consisting of short circuit stub transmission line and inter digital capacitors on a commercial substrate having relative dielectric constant 4.7 and 1.6 mm of thickness. A sample filter is designed based upon the theory presented and it has been simulated with the S-parameters using IE3D software.
Subodh Kumar Singhal, Deepak Sharma, and Ram Mehar Singh Dhariwal
IEEE
This paper presents an optimum distributed microstrip structure highpass filter having a cutoff frequency 1.3 GHz. The distributed elements used for this design are such as commensurate (equal electrical length) transmission line elements. The proposed design consists of shorted circuited stub microstrip transmission lines on a commercial substrate (RT/D 5880) with a relative dielectric constant 2.2 and 1.57 mm thickness. This filter exhibits a highpass band with steep cutoff. A sample filter is designed based upon the theory presented and it has been simulated with the S-parameters and IE3D software. Advanced computer aided design tools and a high precision thin film process make such filters predictable and repeatable. These filters have less radiation, dispersion and sensitivity to nearby objects.