Ivan Saraiva Silva holds a Bachelor's degree in Electrical Engineering (1989) and a Master's degree in Electrical Engineering (1990) from the Federal University of Paraíba. He earned a Diplôme dÉtudes Approfondies (DEA) in Microelectronics and Microinformatics from Pierre and Marie Curie University (Paris VI) in 1991, and a Ph.D. in Computer Science from the same institution in 1995. From 1996 to 2009, he was a faculty member in the Department of Informatics and Applied Mathematics at the Federal University of Rio Grande do Norte. He is currently a Full Professor in the Department of Computer Science at the Federal University of Piauí. His research interests lie in the field of Computer Science, with an emphasis on Integrated System Design, particularly in the areas of Hardware Accelerator Microarchitecture, Reconfigurable Architectures, Computer Vision Applications, Smart Cities, Vehicular Embedded Systems, and Urban Mobility.
RESEARCH, TEACHING, or OTHER INTERESTS
Hardware and Architecture, Computer Vision and Pattern Recognition, Electrical and Electronic Engineering
66
Scopus Publications
Scopus Publications
Feasibility-Aware Design-Space Exploration of Transparent Coarse-Grained Reconfigurable Architectures Thiago R. B. S. Soares, Ivan S. Silva Electronics Switzerland, 2026 Coarse-Grained Reconfigurable Architectures (CGRAs) execute compute-intensive kernels on a reconfigurable processing mesh. Transparent CGRAs extend this model by generating configurations at runtime and storing them in a dedicated cache, removing compiler dependence and enabling adaptive behavior. Although prior work has explored mapping strategies and mesh scaling, the feasibility of the configuration cache remains unaddressed, as it is commonly treated as a generic storage block. This paper presents a feasibility study of configuration cache organizations and a design-space exploration of Transparent CGRAs, introducing a parameterized cache geometry model that relates cache parameters to the processing mesh and configuration structure. The model enables realistic estimates of area, latency, and energy at the digital system level and is applied to three Transparent CGRAs from the literature and five additional designs covering a wide range of spatial and temporal organizations. The results show that mesh scaling must be balanced with cache feasibility: wide I/O paths and large configurations lead to impractical caches, whereas well-proportioned meshes achieve competitive performance with modest overheads. Under the proposed exploration, selected expanded meshes outperform a two-issue out-of-order processor by up to 1.4× while increasing area by only 14.8% and energy by 2%. These findings demonstrate that Transparent CGRAs are viable, but their scalability depends on a realistic configuration cache design. The proposed parameterized cache model provides a structured and reproducible basis for analyzing transparency overheads and guiding future CGRA designs.
Energy-Efficient Cache Configuration Prediction Using Machine Learning on Basic Blocks Lucas Fernandes Ribeiro, Ivan Saraiva Silva, Ricardo Jacobi 2026 IEEE 17th Latin American Symposium on Circuits and Systems Lascas 2026 Proceedings, 2026 This work presents a methodology for predicting energy-efficient cache configurations through supervised machine learning, using features derived from application execution traces. The approach relies on dynamic instructions extracted from basic blocks, focusing particularly on memory access instructions, which have shown significant influence on performance and energy consumption. The methodology was structured into three main stages: (i) creation of a database and energy model through simulations in gem5 and CACTI; (ii) generation of a feature matrix from dynamic instructions; and (iii) training and evaluation of classification models to associate applications with their most energy-efficient cache configuration. Experiments were carried out considering the entire instruction set, only memory access instructions, and the most representative basic blocks. Results demonstrate that reducing the feature space to the most important basic blocks and memory instructions maintains high classification accuracy while significantly reducing model complexity. Although the scope of this work is static reconfiguration, the findings highlight the potential of the proposed methodology as a first step toward enabling dynamic cache reconfiguration in embedded systems, where energy efficiency and lightweight models are critical.
Energy-Efficient Mappings in the Athena CGRA Francisco Júnior, Ricardo Jacobi, Ivan Saraiva Silva 2026 IEEE 17th Latin American Symposium on Circuits and Systems Lascas 2026 Proceedings, 2026 IoT and mobile applications demand high performance with low energy use, motivating alternatives such as transparent Coarse-Grained Reconfigurable Architectures (CGRAs). These accelerators improve efficiency and adapt to workloads at runtime without requiring additional effort from developers. This work extends the ATHENA CGRA to better exploit instruction-level parallelism (ILP) through speculation by enlarging configuration size and modifying the mapping algorithm. We propose two new versions and evaluate them under different speculation levels. Results show execution-focused mapping achieved up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.81 \times$</tex> speedup and 81 % energy savings over a standard processor. The mapped-focused version increased configuration size by 35 % but reduced coverage, while the hybrid version improved some benchmarks and lowered cache energy by 21.6 %, though execution-focused remained superior overall.
CAJU: Convolutional Attentive Joint Units for Infectious Keratitis In Vivo Confocal Microscopy Image Classification Isaac S. S. Ramos, François F. R. Barbosa, Bianca C. Sousa, Ivan S. Silva, Kelson R. T. Aires, Rodrigo M. S. Veras IEEE Access, 2026 Infectious keratitis (IK) is a significant cause of preventable vision loss and necessitates expeditious, dependable etiological assessment. Conventional diagnostics (e.g., corneal scraping, culture, and molecular tests) are often invasive, time-consuming, and resource-dependent, which limits their practicality in routine workflows. As a non-invasive alternative, in vivo confocal microscopy (IVCM) enables high-resolution visualization of corneal microstructures and potential pathogens. However, its interpretation requires specialized expertise and remains subject to inter-observer variability. We hereby propose Convolutional Attentive Joint Units (CAJU), an attention-guided dual-stream pipeline for IK classification from IVCM images. CAJU instantiates complementary CNN backbones and fuses their representations through a transformer-inspired self-attention module, allowing backbone selection according to performance and deployment constraints. The public IVCM-Keratitis dataset was subjected to a series of experiments following the implementation of artifact filtration, encompassing a total of 2,155 images classified into four distinct categories: AK, FK, NSK, and Normal. These experiments were executed through the utilization of a cross-validation approach. Among the evaluated instantiations, CAJU (DenseNet-161 + ResNet-101, w/ SA) demonstrated optimal class-balanced performance, attaining 96.22% precision, 96.01% recall, and 96.03% F1-score, while CAJU (VGG16 + MobileNetV3, w/ SA) attained the maximum accuracy of 97.13%. In order to support interpretability, the present study integrates Grad-CAM and SHAP to localize salient regions and provide class-wise attributions, thereby enabling plausibility checks in both correct predictions and clinically relevant error modes (notably NSK ambiguity). In summary, CAJU offers a dependable and comprehensible framework to facilitate IVCM-based IK diagnosis and to support clinical decision-making, particularly in non-specialized settings.
A Simulation Methodology for Transparent Coarse-Grained Reconfigurable Architectures Thiago R. B. Da S. Soares, Ivan Saraiva Silva Brazilian Symposium on Computing System Engineering Sbesc, 2025 Coarse-Grained Reconfigurable Architectures (CGRAs) are flexible accelerators that exploit instruction-level parallelism with low reconfiguration overhead. Transparent CGRAs extend this model by dynamically generating configurations at runtime, eliminating the need for compiler toolchains and improving adaptability. However, designing transparent CGRAs is a complex task that requires tight integration with the host processor, including access to pipeline stages and specialized mechanisms for synchronization. These requirements often result in highly customized, non-portable implementations that hinder reproducibility and design exploration. Moreover, existing CGRA simulation tools are poorly suited for transparent models, as they rely on static configuration generation and code annotations. To address this gap, we present a simulation methodology specifically tailored for transparent CGRAs. The proposed system models runtime profiling, mapping, and execution using a modular architecture. It supports customizable topologies, speculation levels, mapping algorithms, and processing element capabilities. To demonstrate its capabilities, we simulated eight transparent CGRA models under a unified setup and analyzed the impact of topology, available operations, memory integration, and speculation on system performance. The results demonstrate the framework’s effectiveness for performance evaluation and design space exploration in transparent CGRAs. Additionally, we analyzed the memory system and its impact on performance, area, and energy consumption.
X4-RARE: Revisiting the X4CP32 Coarse-Grained Reconfigurable Architecture Model Ivan Saraiva Silva, Francisco Carlos Silva Junior Proceedings of IEEE Computer Society Annual Symposium on VLSI Isvlsi, 2023 To improve reconfigurable architectures' programmability, a CGRA named X4CP32 was proposed in early 2003. With two execution modes (programming execution mode and reconfigurable execution mode), X4CP32 offered an architectural model providing support to use the array through programming or configuration. In other words, a statical or dynamical procedure defines the processing elements' operations. This paper revisits this CGRA design using modern techniques and tools, notably the GEM5 simulator, the McPAT framework, and CACTI. Also, a hardware unit providing transparent and dynamic reconfiguration was incorporated. Furthermore, the design replaced an unknown and naive embedded microprocessor using RISC-V. Using a modern embedded processor, transparent and dynamic reconfiguration, and a thin array allows the design of a reconfigurable multicore able to execute up to 88% faster and with 55% less energy than a regular multicore. (Abstract)
Evaluating a Machine Learning-based Approach for Cache Configuration Lucas Ribeiro, Ricardo Jacobi, Francisco Junior, Jones Yudi da Silva, Ivan Saraiva Silva 2022 IEEE 13th Latin American Symposium on Circuits and Systems Lascas 2022, 2022 As the systems perform progressively complex tasks, the search for energy efficiency in computational systems is constantly increasing. The cache memory has a fundamental role in this issue. Through dynamic cache reconfiguration techniques, it is possible to obtain an optimal cache configuration that minimizes the impacts of energy losses. To achieve this goal, a precise selection of cache parameters plays a fundamental role. In this work, a machine learning-based approach is evaluated to predict the optimal cache configuration for different applications considering their dynamic instructions and a variety of cache parameters, followed by experiments showing that using a smaller set of application instructions it is already possible to obtain good classification results from the proposed model. The results show that the model obtains an accuracy of 96.19% using the complete set of RISC-V instructions and 96.33% accuracy using the memory instructions set, a more concise set of instructions that directly affect the cache power model, besides decreasing the model complexity.
Evaluating the Performance, Energy and Area Tradeoffs of ATHENA in Superscalar Processors Francisco Carlos Silva Junior, Ivan Saraiva Silva, Ricardo Pezzuol Jacobi Proceedings 34th Sbc Sbmicro IEEE ACM Symposium on Integrated Circuits and Systems Design Sbcci 2021, 2021 Coarse-Grained Reconfigurable architectures (CGRA) have been widely used as accelerator, providing energy saving and performance improvements while also offers flexibility to meet different applications requirements. Despite the aforementioned advantages, CGRAs usually consist of many processing elements, which implies area overhead that can be prohibitive to its integration in system with hard area constraint, such as embedded system and mobile devices. To cope with that, this work evaluates a CGRA for systems with hard area constraint called ATHENA (A Thin rEcoNfigurable Architecture). The thinness concept consists of a CGRA that uses considerably less processing elements than the CGRAs found in the literature. ATHENA is attached to a superescalar processor and is dynamically mapped. A design space exploration on ATHENA and the superescalar processor is carried out to evaluate the different area, energy and performance tradeoffs that these solutions can deliver. The results shows that, even using fewer processing elements, ATHENA was able to speed up to 2.43x while saving up to 32% of energy. When compared with other dynamically mapped CGRAs of the state of the art, ATHENA is up to 4x smaller and provides competitive performance.
Optimized method for locating the source of voltage sags Jose Carlos Filho, Fabbio Anderson da Silva Borges, Ricardo de Andrade Lira Rabelo, Ivan Saraiva Silva, Antonio Oseas de Carvalho Filho Journal of Communications Software and Systems, 2021 Short-Duration Voltage Variations (SDVVs) are the power quality disturbances (PQD) that mainly affect industrial systems, and are originated for various reasons, in particular short circuits over large areas, even those originating in remote points of the electrical system. The location problem aims to indicate the area or region or distance from the substation that is connected to the source causing the voltage sags, and is a fundamental task to ensure good power quality. One of the strategies used to determine the location of sources causing SDVVs and for an implementation of machine learning algorithms in modern distribution networks, called Smart Grids. Monitoring a Smart Grid plays a key role, however mostly it generates a large volume of data (Big Data) and as a result, multiple challenges arise due to the properties of this data such as volume, variety and velocity. This work presents an optimization through genetic algorithm to select meters which already exist in the Smart Grid, using a voltage sag location method in order to reduce the data obtained and analyzed throughout the localization process. Optimization was evaluated through a comparison with a non-optimized localization method, this comparison showed a difference between the hit rates of less than 1%.
UVMP: Virtualizable multi-core platform Ivan Saraiva Silva, Ramon Nepomuceno, Tackyss Mafuta, Eeugenio S. Carvalho 38th Latin America Conference on Informatics Clei 2012 Conference Proceedings, 2012
DDR SDRAM memory controller for digital TV decoders Hadley M. Siqueira, Ivan S. Silva, Marcio E. Kreutz, Edgard F. Correa Proceedings 2011 Brazilian Symposium on Computing System Engineering Sbesc 2011, 2011
Exploring memory organization in virtual MP-SoC platforms Bruno Cruz Oliveira, Márcio Eduardo Kreutz, Edgard de Faria Corrêa, Ivan Saraiva Silva Sbcci 10 Proceedings of the 23rd Symposium on Integrated Circuits and Systems Design, 2010
Using NoC routers as processing elements Sílvio Fernandes, Bruno C. Oliveira, Ivan Saraiva Silva Proceedings of the 22nd Symposium on Integrated Circuits and Systems Design Sbcci 2009, 2009
RoSA: A reconfigurable stream-based architecture Monica Magalhaes Pereira, Bruno Cruz de Oliveira, Ivan Saraiva Silva Proceedings Sbcci 2007 20th Symposium on Integrated Circuits and System Design, 2007
High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard Proceedings IEEE International Symposium on Circuits and Systems, 2006
Papílio cryptography algorithm Frederiko Stenio de Araújo, Karla Darlene Nempomuceno Ramos, Benjamín René Callejas Bedregal, Ivan Saraiva Silva Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 2004
