Gaurav Saini

Scopus Publications

Performance investigation of junctionless nanosheet FET with dual-k sidewall spacer using numerical simulations
Sonia Saini, Gaurav Saini
International Journal of Electronics, 2026
2-D Analytical Surface Potential Modeling and Simulation-Based Optimization of GoP-HD-DMDG-TFET for Enhanced Performance
Nisha Yadav, Sunil Jadav, Gaurav Saini
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2026
This work presents a comprehensive surface potential analysis of the Gate-over-Pockets Hetero-Dielectric Dual-Metal Double-Gate Tunnel Field-Effect Transistor (GoP-HD-DMDG-TFET). The impact of pockets, dielectric thickness and permittivity, gate material work function, silicon body thickness, and gate and drain voltages are taken into account. An analytical model developed using the 2D Poisson’s equation, is validated against Sentaurus TCAD simulations. The impact of critical design parameters on the performance of GoP-HD-DMDG-TFET is investigated. The influence of pocket length (Lpoc), tunneling-to-auxiliary gate length ratio (Ltunn : Laux), pocket thickness (tpoc) and work function variation is systematically analyzed to optimize device performance for improved subthreshold behavior, ON-current, and Ion/Ioff ratio. Results indicate that larger Lpoc indicates a trade-off between improved ON-state performance and increased leakage current, with reduced Subthreshold Swing (SS). Moreover, tuning the tunneling-to-auxiliary gate length ratio (Ltunn : Laux) significantly affects electrostatic control, influencing threshold voltage (Vth) and ON-current (ION). In addition, the pocket thickness (tPOC) is optimized to 4 nm, yielding the steepest subthreshold swing and highest Ion/Ioff ratio. Work function engineering provides an effective approach to modulate the potential barrier and optimize leakage characteristics. These insights highlight the design flexibility of GoP-HD-DMDG-TFET, making it promising candidate for ultra-low-power and high-performance circuit applications.
Dual-gate material H-channel vertical DGTFET: design, simulation and optimisation study
Arashpreet Kaur, Sonia Saini, Gaurav Saini
Semiconductor Science and Technology, 2025
In this study, we introduce the dual-gate material H-channel vertical double-gate tunnel field effect transistor (TFET), designed to achieve a significantly improved current switching ratio ( I ON / I OFF ) while maintaining strong drive current and reduced OFF current. Utilising Sentaurus TCAD simulations, we find that reducing the channel thickness enhances key performance metrics, including ON and OFF currents and subthreshold swing (SS), due to the increased electric field that boosts charge carrier generation at the interface of the source–channel region. To minimise subthreshold leakage, a high- k dielectric is employed between the source–channel and drain regions. Additionally, incorporating a low-value work-function gate material at the source and high-value work-function material at the drain enhances the ON current and I ON / I OFF . This comprehensive analysis optimises geometrical dimensions and doping concentrations, including channel and oxide thickness. Unlike conventional TFETs, our structure features a source surrounded by the channel on three sides, increasing the band-to-band tunneling (BTBT) area and facilitating improved carrier transport. When compared to traditional double- ate TFETs, the proposed device demonstrates a steeper SS, over two orders of magnitude increase in ON current (5.48 × 10 −4 A µ m −1 ), I ON / I OFF of the order of 8.85 × 10 13 and an SS of 22 mV dec −1 . These improvements position our device as an excellent candidate for low-power applications, highlighting its significant potential in electronic device technology.
The Tunnel FET: Fundamentals, Calibration, and Simulation
Nisha Yadav, Sunil Jadav, Gaurav Saini
Nanoelectronics Fundamentals Advances and Applications, 2025
The tunnel field effect transistor (TFET) is the promising next-generation nanoscale transistor as it can provide steep sub-threshold swing characteristics ( SS < 60 mV/decade). This chapter begins with the challenges faced in metal oxide field effect transistor (MOSFET) scaling and thus the need of TFETs. Followed by origin of TFETs, the chapter underlines the fundamentals of a TFET and its working principle. In contrast to MOSFET, TFETs employs Band-To-Band Tunneling (BTBT) which has been explained in detail in this chapter. Following the technological advancements in the TFET structure, the chapter further covers the calibration of TFET from the experimental data using Sentaurus TCAD tool utilizing the dynamic non-local BTBT model. Calibration shows a close match with the experimental data. Finally, using extracted parameters, simulation of a double-gate TFET (DG-TFET) have been discussed in detail with the help of energy band diagrams. Though TFET provides a lot of advantages over its conventional counterparts, in the last, this chapter discusses the key challenges faced by the TFET technology.
Investigating the impact of dielectric modulation on multichannel junctionless Fin and nanosheet BioFET efficacy
Sonia Saini, Gaurav Saini
Physica Scripta, 2025
This study investigates the performance of a dielectric-modulated multi-channel junctionless Fin and nanosheet Bio field effect transistor (BioFET) in the sub-12 nm regime. The effects of various biomolecules on the electrical properties of the FETs are analyzed, revealing that the multi-channel nanosheet BioFET shows higher sensitivity for neutral biomolecules. In the structure of Fin and nanosheet BioFET, a layer of SiO2 followed by HfO2 is used as the bare oxide under metal. This stacking of the oxide layer helps in improving the switching ratio. Electrical characteristics of the BioFETs like transfer chracteristics, output characteristics curve, transconductance, output conductance, ON-state current, switching ratio, and sensitivity analysis are also performed. NS BioFET has 33.3 %, 50% and 28.57% higher subthreshold swing (SS) sensitivity than Fin BioFET and 54.8%, 62.3%, and 58.1 % higher ON-to OFF current ratio sensitivity at k = 3, 5 and 7 respectively. Gate all-around (GAA) Nanosheet BioFET offers the advantage of better performance over Fin BioFET due to the presence of multichannel and large-width nanosheets. The variations in all the characteristics are measured by varying dielectric constants in the range from 1 to 7.
Reversed C-shape Pocket Double Gate TFET with dual-κ Spacers
Arashpreet Kaur, Devang Kailashkumar Vekariya, Gaurav Saini
Indian Journal of Pure and Applied Physics, 2025
The study delves into the evaluation of the Double Gate Tunnel Field-effect Transistors (DGTFET) structures, Reversed C-shape Pocket TFET (RCSP-TFET), and RCSP-TFET with dual-k spacers. The TFET supports current generation through band-to-band tunneling among source/drain and channel regions. By strategically placing the three n+ pockets nearby the source-channel region, the tunneling barrier width is lowered and the current is increased in the ON-state. Subsequent to the calibration of the DGTFET utilizing diverse tunneling models, a comprehensive evaluation of the performance of the RCSP-TFET is undertaken. This assessment is executed through the meticulous optimization of the thickness and length of the n+ pocket, thereby ensuring precise and dependable outcomes. Furthermore, the spacer walls comprised of an amalgamation of high-k and low-k dielectrics is intended to augment the performance of the device. This approach seeks to optimize efficacy and improve operational capabilities. The optimized structure reveals a higher ON-state current (ION)= 7.0 x 10-5 (A/µm), the ON-OFF current ratio (ION/IOFF) , Ambipolar Current (IAmb)= 2.1x 10-13 (A/µm), reduced subthreshold swing (SS)=11.09 mV/decade) in the RCSP-TFET structure with dual-k spacers. The results imply the potential feasibility of the RCSP-TFET with dual-k spacers as a compelling choice for next-generation semiconductor technology.
Linearity performance and harmonic distortion analysis of gate-over-pockets hetero-dielectric dual-metal-double-gate TFET for RF applications
Nisha Yadav, Sunil Jadav, Gaurav Saini
Micro and Nanostructures, 2025
A Comparative Study of Deep Learning Approaches for Early Detection of Sugarcane Diseases
Aryan Kumar, Gaurav Saini
Procedia Computer Science, 2025
Sugarcane, being one of the essential crops for the Indian agricultural economy, that has a significant contribution to the overall agricultural ecosystem of the country. However, the cultivation faces threats from variety of diseases and if, not treated in time bound fashion then it might result in poor yield and low quality, causing financial loss to the farmers. This study explores various approaches using deep learning to detect diseases that are affecting sugarcane cultivation. A dataset of over 6670 images across five classes (healthy, red rot, mosaic, rust, and yellow leaf) is taken. This study compares the performance of several deep learning models, including VGG-19, MobileNet-V2, EfficientNet, and Vision Transformer, with image processing techniques. Transfer learning is used with pre-trained models trained on the ImageNet dataset, and the Vision Transformer is fine-tuned during training. In this study, we found that Vision Transformer outperformed other deep learning models by achieving an accuracy of 98.0% and among the CNN models EfficientNet achieved an accuracy of 96.7%. The comparative analysis highlights the potential of various deep learning approaches for accurate disease detection in sugarcane cultivation. The research contributes to sustainable agricultural practices by providing a framework for early disease identification and prevention of crop losses through deep learning techniques.
Dual Pocket Step Channel TFET for Improved Low-Power Performance
Abhinav Rajyan, Gaurav Saini
Nano Fet Devices Miniaturization Simulation and Applications Part 1, 2025
In this chapter, we introduce a novel Tunnel Field-Effect Transistor (TFET) structure explicitly engineered for low-power applications. The proposed TFET structure offers an improved ION/IOFF current ratio and reduced subthreshold swing values, making it highly suitable for energy-efficient electronic devices. The design achieves a stepped channel by incorporating drain underlapping and channel engineering techniques, effectively reducing ambipolarity current. The proposed structure outperforms conventional TFETs with a 71% smaller average subthreshold swing (SS), demonstrating enhanced efficiency. These improvements address the demand for energy-efficient devices in fields such as portable electronics and the Internet of Things (IoT), demonstrating the innovative TFET structure's potential for low-power applications.
Steep subthreshold swing Double - Gate tunnel FET using source pocket engineering: Design guidelines
Nisha Yadav, Sunil Jadav, Gaurav Saini
Micro and Nanostructures, 2024
Drain Source-Engineered Double-Gate Tunnel FET for Improved Performance
Arashpreet Kaur, Gaurav Saini
Journal of Electronic Materials, 2024
Improving On-state current and Ambipolarity of TFET using Gate-Drain and Gate Dielectric Engineering
Gaurav Saini, Avinash Ganta
Indian Journal of Pure and Applied Physics, 2024
Performance Comparison of Junctionless FinFET with Nanosheet FET and Device Design Guidelines
Sonia Saini, Gaurav Saini
Indian Journal of Pure and Applied Physics, 2024
A Systematic Investigation of Dual Material Gate TFET for Improved Performance
Gaurav Saini, Durga Prasad Miriyala
Indian Journal of Pure and Applied Physics, 2024
SystemVerilog Based Design of an RV32I Compliant RISC-V Processor Core
Abhinav Rajyan, Gaurav Saini
2024 5th IEEE Global Conference for Advancement in Technology Gcat 2024, 2024
Comparative Study of Nanowire FET & Internal Gate Nanowire FET
Abhinav Rajyan, Matin, Gaurav Saini
Proceedings 2nd IEEE International Conference on Device Intelligence Computing and Communication Technologies Dicct 2024, 2024
Design and Analysis of a Novel Asymmetric Source Dual-Material DG-TFET with Germanium Pocket
Arashpreet Kaur, Gaurav Saini
Silicon, 2023
Fully Depleted Planar Bi-layer Junctionless Transistor for Future Technology Node
Gaurav Saini, Trailokya Nath Sasamal
Quantum Dot Cellular Automata Circuits for Nanocomputing Applications, 2023
Enhancing the Performance of DG-TFET Using Si/Ge Source n+Pocket Engineering
Sonakshi Beniwal, Gaurav Saini
2023 International Conference on System Computation Automation and Networking Icscan 2023, 2023
A Review on Role of Epitaxial Engineering in Improving the Drive Current and Subthreshold Swing in Area Scaled Tunnel FETs
Nisha Yadav, Sunil Jadav, Gaurav Saini
2023 International Conference on Computer Electronics and Electrical Engineering and their Applications Ic2e3 2023, 2023
Impact of Gate Length and Doping Variation on the DC and Analog/RF Performance of sub - 3n m Stacked Si Gate-All-Around Nanosheet FET
Nisha Yadav, Sunil Jadav, Gaurav Saini
Silicon, 2023
High-Speed Comparator and Parity Generator Towards Simplified Clocking Circuit in QCA Technology
Trailokya Nath Sasamal, Hari Mohan Gaur, Vineet Jaiswal, Gaurav Saini, Ashutosh Kumar Singh
Quantum Dot Cellular Automata Circuits for Nanocomputing Applications, 2023
Geometrical Variability Impact on the Performance of Sub - 3 nm Gate-All-Around Stacked Nanosheet FET
Nisha Yadav, Sunil Jadav, Gaurav Saini
Silicon, 2022
DC and Analog/RF Performance Analysis of Multi-Bridge Channel FET with Variation in Gate Work Function
Nisha Yadav, Sunil Jadav, Gaurav Saini
2022 International Conference for Advancement in Technology Iconat 2022, 2022
High Speed Comparator and Parity generator in QCA based on optimal XOR structure
Trailokya Nath Sasamal, Gaurav Saini, Vineet Jaiswal
2022 IEEE 7th Forum on Research and Technologies for Society and Industry Innovation Rtsi 2022, 2022
Design of High Speed and Power Efficient 16 × 8 SRAM Memory Using Improved 4 × 16 Decoder
Ankit Kulshrestha, Sajal Samaiya, Onkar Nath Jha, Gaurav Saini
Lecture Notes in Electrical Engineering, 2022
Study on the negative transconductance behaviour in GaAs/AlGaAs based HEMT
Sujit Kumar Singh, Awnish Kumar Tripathi, Gaurav Saini
Superlattices and Microstructures, 2020
Modeling of dual material surrounding split gate junctionless transistor as biosensor
Muktasha Maji, Gaurav Saini
Superlattices and Microstructures, 2019
Design of Carry Select Adder with Online Testability Using Reversible Gates
P. Sudheer Kumar Reddy, Gaurav Saini
2019 4th IEEE International Conference on Recent Trends on Electronics Information Communication and Technology Rteict 2019 Proceedings, 2019
L-shaped tunnelling field effect transistor with hetero-gate dielectric and hetero dielectric box
Sonakshi Beniwal, Gaurav Saini
Proceedings of the International Conference on Trends in Electronics and Informatics Icoei 2019, 2019
Performance Enhancement of Non-uniformly Doped Junctionless Transistors by Gate and Dielectric engineering
Muktasha Maji, Gaurav Saini
Proceedings of 3rd International Conference on 2019 Devices for Integrated Circuit Devic 2019, 2019
Pedestrian Detection System with a Clear Approach on Raspberry Pi 3
S. Sai Charan, Gaurav Saini
Proceedings of the International Conference on Inventive Research in Computing Applications Icirca 2018, 2018
An Efficient Model to Count Objects in Motion by Trading off the Area Threshold
Upasna Singh, Gaurav Saini, Narendra Singh
Proceedings of the International Conference on Inventive Research in Computing Applications Icirca 2018, 2018
Improving the performance of dual-k spacer underlap Double Gate TFET
Abhinav Chauhan, Gaurav Saini, Pavan Kumar Yerur
Superlattices and Microstructures, 2018
Impact of channel engineering on double gate junction less transistor for improved analog performance
Sheetal Rani, Gaurav Saini
2018 International Conference on Emerging Trends and Innovations in Engineering and Technological Research Icetietr 2018, 2018
Spacer Engineered Junction-Less Transistor: A Device Circuit Co-Design Study for Ultra-Low Power Applications
Neha Saini, Gaurav Saini
Proceedings of the 2nd International Conference on Intelligent Computing and Control Systems Iciccs 2018, 2018
Sensitivity Analysis of Junctionless FinFET for Analog Applications
Sachindra Bharti, Gaurav Saini
Proceedings of the 2nd International Conference on Intelligent Computing and Control Systems Iciccs 2018, 2018
Using Source Side Channel Engineering on Junctionless Transistor for Improved Analog Performance
Avinash Kranti, Rahul Shandilya, Gaurav Saini
2018 International Conference on Recent Innovations in Electrical Electronics and Communication Engineering Icrieece 2018, 2018
Cluster-based scheduling algorithm
K P Alex Joseph, Gaurav Saini
2018 3rd IEEE International Conference on Recent Trends in Electronics Information and Communication Technology Rteict 2018 Proceedings, 2018
A Graded Channel Dual-Material Gate Junctionless MOSFET for Analog Applications
Varsha Pathak, Gaurav Saini
Procedia Computer Science, 2018
Analog performance investigation of double gate junctionless transistor using spacer layer engineering
Nalineesh Chahal, Gaurav Saini
8th International Conference on Computing Communications and Networking Technologies Icccnt 2017, 2017
Effect of random dopant fluctuation in nanoscale junctionless FinFET using low and high-k spacers
Sushma Dwivedi, Gaurav Saini
8th International Conference on Computing Communications and Networking Technologies Icccnt 2017, 2017
Random dopant induced threshold voltage variation analysis of asymmetric spacer FinFETs
Navdeep Gehlawat, Gaurav Saini
Proceedings International Conference on Trends in Electronics and Informatics Icei 2017, 2017
Study of self-heating effects on fully depleted SOI MOSFETs with BOX layer engineering
Sudhanshu Kumar Pandey, Gaurav Saini
Proceedings International Conference on Trends in Electronics and Informatics Icei 2017, 2017
Improving the subthreshold performance of junctionless transistor using spacer engineering
Gaurav Saini, Sudhanshu Choudhary
Microelectronics Journal, 2017
Analog/RF performance of source-side only dual-k sidewall spacer trigate junctionless transistor with parametric variations
Gaurav Saini, Sudhanshu Choudhary
Superlattices and Microstructures, 2016
Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs
Gaurav Saini, Sudhanshu Choudhary
Microelectronics Journal, 2016
Heterojunction tunnel FET with Heterodielectric BOX
Mohammad Madhini, Gaurav Saini
International Conference on Communication and Signal Processing Iccsp 2016, 2016
Investigation of trigate JLT with dual-k sidewall spacers for enhanced analog/RF FOMs
Gaurav Saini, Sudhanshu Choudhary
Journal of Computational Electronics, 2016
Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance
Gaurav Saini, Sudhanshu Choudhary
Journal of Computational Electronics, 2016
Design of a novel regulated cascode current mirror
Devendra Jakhar, Gaurav Saini
IEEE International Conference on Computer Communication and Control Ic4 2015, 2016
A stable and power efficient SRAM cell
Rohit, Gaurav Saini
IEEE International Conference on Computer Communication and Control Ic4 2015, 2016
Design of a novel regulated cascode current mirror
Sumit Laha, Rinita Roy
2015 International Conference on Computing Communication and Security Icccs 2015, 2016
Enhanced cascode node impedance to the improved recyclic folded cascode OTA
P. Dillep, Gaurav Saini
Proceedings of 2014 IEEE International Conference on Advanced Communication Control and Computing Technologies Icaccct 2014, 2015
Stacked keeper with body bias: A new approach to reduce leakage power for low power VLSI design
K. N. Bhargav, A. Suresh, Gaurav Saini
Proceedings of 2014 IEEE International Conference on Advanced Communication Control and Computing Technologies Icaccct 2014, 2015
Impact of radial compression on the conductance of carbon nanotube field effect transistors
SUDHANSHU CHOUDHARY, GAURAV SAINI, S. QURESHI
Modern Physics Letters B, 2014
Leakage behavior of underlap FinFET structure: A simulation study
Gaurav Saini, Ashwani K Rana, Pankaj Kr. Pal, Sunil Jadav
2010 International Conference on Computer and Communication Technology Iccct 2010, 2010
Low power high throughput current mode signalling technique for global VLSI interconnect
Sunil Jadav, Gargi Khanna, Ashok Kumar, Gaurav Saini
2010 International Conference on Computer and Communication Technology Iccct 2010, 2010
New low-power techniques: Leakage feedback with stack & sleep stack with keeper
Pankaj Kr. Pal, Rituraj S. Rathore, Ashwani K. Rana, Gaurav Saini
2010 International Conference on Computer and Communication Technology Iccct 2010, 2010

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