Dr. C Gangaiah Yadav

@cbit.edu.in

Associate Professor, ECE
Chaitanya Bharathi Institute of Technology

Dr. C Gangaiah Yadav


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https://researchid.co/ganga486

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering, Signal Processing
10

Scopus Publications

55

Scholar Citations

2

Scholar h-index

1

Scholar i10-index

Scopus Publications

  • FPGA Implementation of a Fault-Tolerant Low-Latency Reversible ALU Using Hybrid Parity-Preserving IG-NFT Logic Gates in Verilog HDL
    Kattubadi Abdul Raseed, S. Rambabu, Manubolu Venugopal Naidu, C. Gangaiah Yadav, Bikkili Alekya Himabindu
    Proceedings of the 4th International Conference on Intelligent Data Communication Technologies and Internet of Things Idciot 2026, 2026
    This paper presents a fault-tolerant, low-latency reversible Arithmetic Logic Unit (ALU) designed using hybrid parity-preserving IG and NFT gates in Verilog HDL. Reversible computing minimizes energy dissipation and enables quantumcompatible designs, while parity preservation ensures on-chip error detection. The proposed ALU performs addition, subtraction, AND, and XOR operations with reduced quantum cost, fewer garbage outputs, and lower logic depth compared to conventional and earlier reversible ALUs, such as the hybrid Fredkin–Feynman ALU, Peres–HNG ALU. Synthesized on an Xilinx Artix-7 FPGA board with the VIVADO simulation tool, the design exhibits notable improvements in power efficiency, logic utilisation, and fault tolerance. Scalability for multi-bit operations and compatibility with quantum frameworks make the architecture suitable for low-power embedded systems, IoT processors, and cryptographic applications.
  • An IoT Based Smart Speaking Device for Mute People
    Gangaiah Yadav Chelluboina, Lakshmi Kiran Mukkara, Imam Basha Shaik, Ajay Kumar Manchala, Vulusala Divya Manjari, Nandyalapeta Shaik Mahammad Jubair
    Aip Conference Proceedings, 2025
  • Design of a Squaring Architecture Based on Yavadunam Sutra of Vedic Mathematics
    C.Gangaiah Yadav, G.Sreenivasula Reddy, K.Venkata Subba Reddy
    Proceedings of International Conference on Visual Analytics and Data Visualization Icvadv 2025, 2025
    The Yavadunam Sutra, a computational method from Vedic mathematics renowned for its effectiveness in squaring numbers, served as the inspiration for the VISI design of a squaring architecture. The goal is to create a VLSI architecture that improves computational speed and efficiency by utilizing the Yavadunam Sutra's parallel processing and optimization ideas. Important parts of the architecture, including registers, adders, and multiplication units, will be designed and optimized. While optimizing performance measures like speed and accuracy, special focus will be paid to reducing power consumption and space use. Modern VLSI design tools and methodologies will be used to implement the design. The goal is to investigate and evaluate the possible advantages of incorporating ideas from Vedic mathematics into VLSI architectures for computational tasks, with a particular emphasis on squaring operations. By integrating fundamental mathematical concepts and refining hardware implementations for increased performance and efficiency.
  • Cloud based prediction of epileptic seizures using real-time electroencephalograms analysis
    Gousia Thahniyath, Chelluboina Subbarayudu Gangaiah Yadav, Rajagopalan Senkamalavalli, Shanmugam Sathiya Priya, Stalin Aghalya, Kuppireddy Narsimha Reddy, Subbiah Murugan
    International Journal of Electrical and Computer Engineering, 2024
    This study aims to improve the accuracy of epileptic seizure prediction using cloud-based, real-time electroencephalogram analysis. The goal is to build a strong framework that can quickly process electroencephalogram (EEG) data, extract relevant features, and use advanced machine learning algorithms to predict seizures with high accuracy and low latency by taking advantage of cloud platforms' computing power and scalability. The main objective is to provide patients and their caregivers with timely notifications so that they may control epilepsy episodes proactively. The goal of this project is to improve the lives of people with epilepsy by reducing the impact of seizures and improving treatment results via real-time analysis of EEG data. Cloud computing also allows the suggested seizure prediction system to be more accessible and scalable, meaning more people worldwide could benefit from it. This section discusses the results from five separate datasets of patients with epileptic seizures who underwent EEG analysis with the following details as frontopolar (FP1, FP2), frontal (F3, F4), frontotemporal (F7, F8), central (C3, C4), temporal (T3, T4), parieto-temporal (T5, T6), parietal (P3, P4), occipital (O1, O2), time (HH:MM:SS).
  • The effect of resistive open faults on SRAM
    C. Gangaiah Yadav, B. Saroja, V. Jahnavi, V. Dilli Kumari, M. Geethanjali, R. Gnana Prasanna
    Aip Conference Proceedings, 2024
  • Impact of Length and Width Ratio on SRAM
    C. Gangaiah Yadav, B. Saroja, M. Lakshmi Kiran
    2nd International Conference on Intelligent Cyber Physical Systems and Internet of Things Icoici 2024 Proceedings, 2024
    Recent IC based design technologies most unfortunately are affected by several undesired side effects. An increased level of the leakage currents is the main reason of the undesired side effects. There are two types of Random-Access Memories (RAM). These are Static Random Access Memory and Dynamic Random Access Memory. Static RAM (SRAM) design with more than five transistors but Dynamic RAM (DRAM) design with single transistor. The SRAM design to operate in Read and Write mode operations should have stability and reliability on Read and Write operations, respectively. The Read Static Noise Margin (RSNM) and Write Static Noise Margin (WSNM) are commonly using matrices for deriving read stability and write ability of SRAMs. The Length and Width of the transistors which are used in design of SRAM cell shows more impact on operational parameters. During the fabrication of these low power SRAMs induces different kind of faults. One of the significant faults is resistive open fault.it degrades conduction between two nodes of the circuit. It causes delay faults. In this paper discussed about effect of W/L ratio on 6 transistor SRAM described and compared with existing circuit.
  • Comparison of Read Stability and Write Ability of Low Power Nanometric SRAMs
    C. Gangaiah Yadav, C. Keerthi, A. Kiran Kumari
    Lecture Notes in Networks and Systems, 2023
  • IoT Enabled Microgrid System for Enhancing Power Quality Using Adaptive Neuro-Fuzzy Control Algorithm
    M. Venkatesh, V. G. Sivakumar, C. Gangaiah Yadav, B. Gopi, N. Malathi, S. Velmurugan
    2023 International Conference on Power Energy Environment and Intelligent Control Peeic 2023, 2023
    Microgrid systems have emerged because of the rising need for efficient and dependable power supply, as well as the widespread use of internet of things (IoT) technologies. However, nonlinear loads, fluctuations in voltage, and harmonics are often present in these systems, resulting in poor power quality. This research proposes a Unified Power Quality Conditioner (UPQC) system to overcome these obstacles. The adaptive neuro-fuzzy inference system is employed with IoT connection that allows the UPQC to dynamically adapt in real-time to power quality issues, keeping important loads supplied with clean, uninterrupted power. The suggested system is shown to be beneficial in preventing power outages by providing continuous monitoring, control, and problem diagnostics. The results set the way for future power supply solutions that are more efficient and dependable by adding to a set of information regarding methods to improve power quality in microgrid systems.
  • Impact of resistive open faults on inverter chain and 7t sram
    C.Gangaiah Yadav*, , K.S.Vijula Grace, and
    International Journal of Recent Technology and Engineering, 2019
    An aggressive scaling of the technology and the increasing the number of the transistor counts are the major challenge of the design of the Integrated Circuit (IC). As well as interconnection lines and resistive opens have become a problem in modern nanometre technologies. The resistive open faults denote degradation in the connectivity within a circuit’s interconnects because of unavoidable manufacturing failures in both current and developing technologies. The resistive open fault is an imperfect circuit connection that can be modelled as a defect resistor between two circuit nodes. The Resistive open faults will not cause function fault immediately. But, it will cause the delay fault and cannot employ the design of voltage to survey. In this research, find the impact of resistive open fault in the 7-Transistor (7T) SRAM cell design and inverter chain. The proposed 7T SRAM cell design and inverter chain is implemented in 45nm technology with cadence library. The main objective of this proposed research work is to efficiently detect impact of resistive open faults and reduces delay and static and dynamic power of 7T SRAM cell design and inverter chain.
  • Resistive open fault and detection methods for low power nanometric integrated circuits
    Gangaiah C. Yadav, Vijula K. S. Grace
    Journal of Computational and Theoretical Nanoscience, 2019
    Resistive open fault represents degradation in conductivity within a circuit interconnection. Due to this manufacturing failure occurs in IC interconnection. Such fault causes performance failures and reliability risk. This paper presents the analysis various detection methods for resistive open faults. And detectable resistance range versus VDD varies with the test speed also observes. Depending on test speed and small delay faults Multi-VDD is required for detection of ROFs.

RECENT SCHOLAR PUBLICATIONS

  • Design of a Squaring Architecture Based on Yavadunam Sutra of Vedic Mathematics
    CG Yadav, GS Reddy, KVS Reddy
    2025 International Conference on Visual Analytics and Data Visualization … , 2025
    2025
  • An IoT based smart speaking device for mute people
    CG Yadav
    AIP Conference Proceedings 3237 , 2025
    2025
  • Novel Method of Highly Secured Image Encryption Technique
    CG Yadav
    Journal of Information Systems Engineering and Management 10 (23), 460-471 , 2025
    2025
  • Cloud based prediction of epileptic seizures using real-time electroencephalograms analysis.
    G Thahniyath, CSG Yadav, R Senkamalavalli, SS Priya, S Aghalya, ...
    International Journal of Electrical & Computer Engineering (2088-8708) 14 (5) , 2024
    2024
    Citations: 45
  • Impact of Length and Width Ratio on SRAM
    CG Yadav, B Saroja, ML Kiran
    2024 Second International Conference on Intelligent Cyber Physical Systems … , 2024
    2024
    Citations: 1
  • The effect of resistive open faults on SRAM
    CG Yadav, B Saroja, V Jahnavi, VD Kumari, M Geethanjali, RG Prasanna
    AIP Conference Proceedings 3028 (1), 020002 , 2024
    2024
    Citations: 2
  • CAREFUL QUALITY AGRICULTURE (CQA) FIELD
    DCG Yadav
    IN Patent 51/2,023 , 2023
    2023
  • IoT Enabled Microgrid System for Enhancing Power Quality Using Adaptive Neuro-Fuzzy Control Algorithm
    M Venkatesh, VG Sivakumar, CG Yadav, B Gopi, N Malathi, ...
    2023 International Conference on Power Energy, Environment & Intelligent … , 2023
    2023
    Citations: 1
  • ALCOHOL DETECTION USING SMART HELMET SYSTEM
    RGP Dr.C.Gangaiah Yadav, V.JAHNAVI, V.DILLIKUMARI, M.GEETHANJALI
    International Journal of Creative Research Thoughts 11 (4), a413-a418 , 2023
    2023
  • Wearable Reader for visually Impaired People
    CG Yadav
    IN Patent 05/2,023 , 2023
    2023
  • Comparison of Read Stability and Write Ability of Low Power Nanometric SRAMs
    CG Yadav, C Keerthi, AK Kumari
    Cyber Technologies and Emerging Sciences: ICCTES 2021, 127-132 , 2022
    2022
    Citations: 2
  • Electronics Measurements and Instrumentation
    CG Yadav
    2022
  • Intelligent PV Based Hybrid Fast EV Commercial Charging Station
    CG Yadav
    IN Patent 35/2,021 , 2021
    2021
  • Design of Low Power 6T Sram with and without ROFs
    DKSVG C.Gangaiah Yadav
    International Journal of Recent Technology and Engineering 8 (6), 3531-3536 , 2020
    2020
    Citations: 1
  • Impact of Resistive Open Faults on Inverter Chain and 7t Sram
    CG Yadav, KSV Grace
    International Journal of Recent Technology and Engineering 8 (3), 559-563 , 2019
    2019
    Citations: 1
  • Resistive Open Fault and Detection Methods for Low Power Nanometric Integrated Circuits
    GC Yadav, VKS Grace
    Journal of Computational and Theoretical Nanoscience 16 (2), 400-402 , 2019
    2019
    Citations: 2
  • Solar and Wind Power Chargeable Vehicles
    CGY B.Saroja
    Journal of Emerging Technologies and Innovative Research 6 (1), 107-112 , 2019
    2019
  • Design and Analysis of 45nm 8T SRAM
    CG Yadav
    Journal of Emerging Technologies and Innovative Research 5 (12), 511-513 , 2018
    2018
  • Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression
    DKSVG C.Gangaiah Yadav
    International Journal of Research in Advent Technology 6 (11), 3265-3270 , 2018
    2018
  • Implicit Analysis of Various Detection Methods for Resistive Open Faults in Low Power Nanometric ICs
    DKSVG C.Gangaiah Yadav
    IEEE-EECCMC-2018 1 (XI), 480-482 , 2018
    2018

MOST CITED SCHOLAR PUBLICATIONS

  • Cloud based prediction of epileptic seizures using real-time electroencephalograms analysis.
    G Thahniyath, CSG Yadav, R Senkamalavalli, SS Priya, S Aghalya, ...
    International Journal of Electrical & Computer Engineering (2088-8708) 14 (5) , 2024
    2024
    Citations: 45
  • The effect of resistive open faults on SRAM
    CG Yadav, B Saroja, V Jahnavi, VD Kumari, M Geethanjali, RG Prasanna
    AIP Conference Proceedings 3028 (1), 020002 , 2024
    2024
    Citations: 2
  • Comparison of Read Stability and Write Ability of Low Power Nanometric SRAMs
    CG Yadav, C Keerthi, AK Kumari
    Cyber Technologies and Emerging Sciences: ICCTES 2021, 127-132 , 2022
    2022
    Citations: 2
  • Resistive Open Fault and Detection Methods for Low Power Nanometric Integrated Circuits
    GC Yadav, VKS Grace
    Journal of Computational and Theoretical Nanoscience 16 (2), 400-402 , 2019
    2019
    Citations: 2
  • Impact of Length and Width Ratio on SRAM
    CG Yadav, B Saroja, ML Kiran
    2024 Second International Conference on Intelligent Cyber Physical Systems … , 2024
    2024
    Citations: 1
  • IoT Enabled Microgrid System for Enhancing Power Quality Using Adaptive Neuro-Fuzzy Control Algorithm
    M Venkatesh, VG Sivakumar, CG Yadav, B Gopi, N Malathi, ...
    2023 International Conference on Power Energy, Environment & Intelligent … , 2023
    2023
    Citations: 1
  • Design of Low Power 6T Sram with and without ROFs
    DKSVG C.Gangaiah Yadav
    International Journal of Recent Technology and Engineering 8 (6), 3531-3536 , 2020
    2020
    Citations: 1
  • Impact of Resistive Open Faults on Inverter Chain and 7t Sram
    CG Yadav, KSV Grace
    International Journal of Recent Technology and Engineering 8 (3), 559-563 , 2019
    2019
    Citations: 1
  • Design of a Squaring Architecture Based on Yavadunam Sutra of Vedic Mathematics
    CG Yadav, GS Reddy, KVS Reddy
    2025 International Conference on Visual Analytics and Data Visualization … , 2025
    2025
  • An IoT based smart speaking device for mute people
    CG Yadav
    AIP Conference Proceedings 3237 , 2025
    2025
  • Novel Method of Highly Secured Image Encryption Technique
    CG Yadav
    Journal of Information Systems Engineering and Management 10 (23), 460-471 , 2025
    2025
  • CAREFUL QUALITY AGRICULTURE (CQA) FIELD
    DCG Yadav
    IN Patent 51/2,023 , 2023
    2023
  • ALCOHOL DETECTION USING SMART HELMET SYSTEM
    RGP Dr.C.Gangaiah Yadav, V.JAHNAVI, V.DILLIKUMARI, M.GEETHANJALI
    International Journal of Creative Research Thoughts 11 (4), a413-a418 , 2023
    2023
  • Wearable Reader for visually Impaired People
    CG Yadav
    IN Patent 05/2,023 , 2023
    2023
  • Electronics Measurements and Instrumentation
    CG Yadav
    2022
  • Intelligent PV Based Hybrid Fast EV Commercial Charging Station
    CG Yadav
    IN Patent 35/2,021 , 2021
    2021
  • Solar and Wind Power Chargeable Vehicles
    CGY B.Saroja
    Journal of Emerging Technologies and Innovative Research 6 (1), 107-112 , 2019
    2019
  • Design and Analysis of 45nm 8T SRAM
    CG Yadav
    Journal of Emerging Technologies and Innovative Research 5 (12), 511-513 , 2018
    2018
  • Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression
    DKSVG C.Gangaiah Yadav
    International Journal of Research in Advent Technology 6 (11), 3265-3270 , 2018
    2018
  • Implicit Analysis of Various Detection Methods for Resistive Open Faults in Low Power Nanometric ICs
    DKSVG C.Gangaiah Yadav
    IEEE-EECCMC-2018 1 (XI), 480-482 , 2018
    2018