Babita Jajodia

@assistant professor

Assistant Professor, Department of Electronics and Communication Engineering
Indian Institute of Information Technology, Guwahati

Babita Jajodia


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https://researchid.co/babitajajodia
I, Dr. Babita Jajodia, am an Assistant Professor in the Department of Electronics and Communications Engineering (ECE) at the Indian Institute of Information Technology Guwahati (IIITG) working from July 2019. Prior to that, I received the Ph.D. degree in VLSI Design from the Indian Institute of Technology Guwahati (IITG). Following that I worked at the Gauhati University Institute of Science and Technology (GUIST) as a guest faculty. My research interests are on VLSI Design for Digital/Analog/Mixed-Signal Systems and Quantum Computing.

EDUCATION

Mixed-Signal VLSI Design (PhD) from Indian Institute of Technology Guwahati

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering, Hardware and Architecture
43

Scopus Publications

222

Scholar Citations

9

Scholar h-index

8

Scholar i10-index

Scopus Publications

  • Division-Free Four-Way Toom-Cook Polynomial Multiplication Architecture for Large Integer Arithmetic on FPGAs and ASICs
    Monalisa Das, Babita Jajodia
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2026
    Polynomial multiplication performs as the most important task and is computationally extensive in cryptographic algorithms. Of the several polynomial multiplications, theoretically, the Toom-Cook multiplication is the most efficient. In this paper, an efficient four-way Toom-Cook (Toom-4) multiplication method has been presented that provides accurate result as the product and can be efficiently implemented in hardware. This is done by eliminating the effects of exact divisions present in the intermediate steps of the computation. In addition to these, the hardware implementation of the proposed work suggests that this multiplication method performs better in terms of resource utilization and delay minimization compared to other existing Toom-4 algorithm methods. Hardware implementation of the proposed Toom-4 multiplication architecture is done using a Virtex-7 FPGA device in Xilinx (now AMD) ISE platform. Here, the hardware implementation of the proposed multiplier is performed for 128 bits, 256 bits, and 512 bits with advantages in the area-time-product (ATP) over previous researches; ATP is the figure of merit in determining the performance of the design. Practically for 512 input bits, the percentage ATP of the proposed design is 98.810%, 23.537% and 57.316% better compared to Toom-2 (Karatsuba) multiplication, Hybrid Toom-2 (Karatsuba-Comba) multiplication, and existing Toom-4 multiplication, respectively. Moreover, ASIC implementation results on United Microelectronics Corporation (UMC) 65-nm technology demonstrate a notable reduction in area-time-product (ATP) and power-time-product (PTP) compared to state-of-the-art works.
  • Interpretable machine learning for diabetes risk prediction: a large-scale analysis of Indian national survey data
    Bhavana Barman, Hari K. Choudhury, Babita Jajodia
    Discover Public Health, 2025
    Background Diabetes is a growing public-health challenge in India, and most Machine Learning (ML) studies use small, clinical datasets with limited interpretability. There remains a gap in applying interpretable ML models to nationally representative data to form policy measures. Objective To develop and interpret ML models for diabetes risk prediction using NFHS-5 dataset, and to validate model-derived risk factors with a traditional regression approach. Methods The study used tree-based ML models to train NFHS-5 data, and analysed 1,087,006 respondents’ data for diabetes prevalence. Based on the existing literature, various features or factors such as socio-demographic, behavioural, and anthropometric variables are included in the estimated models. Also, systematic hyperparameter tuning was performed for optimization. Results Random Forest model performed better in comparison with other alternative models. The SHAP analysis identified age, hypertension, and arm circumference as the major contributors of diabetes prediction. The wealth index and urban residence also contribute significantly to the prediction of diabetes. The estimated logistic regression coefficients and AUC values aligned with the directions and magnitude of the SHAP analysis. Conclusion Interpretable ML on nationally representative survey data yields transparent risk profiles for diabetes, linking socio-economic and clinical factors. Policy-relevant actions include maintaining the screening age of 30 years and prioritizing older/high-risk adults, integrating diabetes checks into hypertension programs, and using arm circumference as a community triage tool. These findings support scalable and data-driven primary-care strategies in India.
  • ATP-Optimized Implementation of Four-Way Toom-Cook Multiplications on FPGAs for Large Integer Arithmetic
    Monalisa Das, Babita Jajodia
    Circuits Systems and Signal Processing, 2025
  • Area and Delay Trade-Offs in Three-Way Toom-Cook Large Integer Multipliers Implemented on FPGAs
    Monalisa Das, Babita Jajodia
    IEEE Transactions on Circuits and Systems I Regular Papers, 2025
    The demand for efficient large integer polynomial multiplications in present day crypto-systems is the need of the hour. Toom-Cook multiplication algorithm being one of the most efficient multiplication algorithm is discussed in this work. The limitations of large integer polynomial multiplications using three-way Toom-Cook (Toom-3) multiplication algorithm and the methods to overcome it are presented in this paper. This is done by implementing two different division-free methods for symmetric Toom-3 multiplication as well as for asymmetric Toom-3 multiplication based on the input operand size (N). Hardware implementations of the proposed multiplication methods are done using Virtex-7 Field Programmable Gate Array (FPGA) device in Xilinx ISE platform. The trade-off between hardware utilization and speed is noted, and the overall performance of the proposed design methods are measured by calculating Area-Time-Product (ATP). Practically, it has been observed that both the proposed Toom-3 multiplication methods performs better compared to the existing state-of-the-art designs.
  • Hybrid Recursive Karatsuba Multiplications on FPGAs
    Monalisa Das, Babita Jajodia
    IEEE Embedded Systems Letters, 2025
    The demand for large integer polynomial multiplications has become increasingly significant in modern cryptographic algorithms. The practical implementation of such multipliers presents a field of research focused on optimizing hardware design concerning space and time complexity. In this letter, the authors propose an efficient polynomial multiplier based on a hybrid recursive Karatsuba multiplication (HRKM) algorithm. The overall performance of the proposed design is evaluated using the area-time-product (ATP) metric. The hardware implementation of the proposed architecture is carried out on a Virtex-7 FPGA device using the Xilinx ISE platform. Hardware implementation results show that the proposed HRKM architecture shows ATP reduction of 67.885%, 70.128%, and 65.869% for 128, 256, and 512 bits, respectively, in comparison to Hybrid Karatsuba (nonrecursive) multiplications.
  • Floating Point Multipliers on FPGAs
    Uttam Singh, Rahul Mundliya, Raushan Maharana, Babita Jajodia
    Proceedings of 6th International Conference on 2025 Devices for Integrated Circuit Devic 2025, 2025
    This work presents IEEE 754 compliant floatingpoint multipliers for various formats: Half Precision (HP), Single Precision (SP), Double Precision (DP), Double Extended Precision (DEP), and Quadruple Precision (QP), with bit lengths of 16, 32, 64, 80, and 128 bits, respectively, implemented on Field Programmable Gate Arrays (FPGAs). The study explores different mantissa multipliers – Optimized Schoolbook Multiplier (OBSM), Hybrid Karatsuba Multiplier (HKM) and Hybrid Recursive Karatsuba Multiplier (HRKM) – to identify the most efficient mantissa multipliers that comply with the IEEE 754 standard and are suitable for floating-point multipliers. Hardware implementations show that the proposed HRKM-based SP and DP floating-point multipliers show a better Area-Time-Product (ATP) performance of 79. 599% and 83. 901%, respectively, in comparison to the latest state-of-the-art work on the AMD Kintex Ultrascale KCU105 FPGA platform.
  • Improved Montgomery Modular Multipliers on FPGAs and ASICs
    Arghya Roy, Raushan Maharana, Sourabh Kumar Singh, Babita Jajodia
    IEEE Embedded Systems Letters, 2025
    This paper presents the design of an Improved Montgomery Modular Multiplier (MMM) employing three large-integer hybrid recursive Karatsuba multipliers (HRKM) with the base cases replaced by Optimized Schoolbook multipliers (OSBM). This method achieves a single-cycle modular multiplier with significantly reduced resource utilization and latency on FPGAs and ASICs. The proposed design is implemented on a Virtex-6 and Virtex UltraScale+ XCVU9P FPGA platform and synthesized using Synopsys Design Compiler for ASIC implementation. Experimental results on the AMD FPGA platform demonstrate a notable reduction in area-time product (ATP) of 92.766% and 95.130% for an improved 256-bit MMM compared to the best state-of-the-art MMMs on the Virtex-6 and Virtex UltraScale+ XCVU9P FPGA platform. Moreover, results of ASIC implementation on United Microelectronics Corporation (UMC) 65nm technology demonstrate a notable reduction in the power time product (PTP) of 22.173% compared to the best state-of-the-art works.
  • Hybrid FSR-based Pseudo-Random Number Generator on FPGA for Encrypting Biometrics
    Keerthana Menon, Goutam Mali, Nalesh S, Babita Jajodia, Kala S
    Proceedings of the International Conference on Microelectronics Icm, 2025
    Biometric data sent over interconnected networks and the cloud need to be safeguarded to ensure their integrity and confidentiality. Random Number Generators (RNGs) produce a stream of random bits that can be used to encrypt the transmitted data. Feedback shift registers (FSRs) are a resource-efficient method to design such number generators. In this work, we propose a secure and resource-efficient Pseudo-Random Number Generator (PRNG) that uses two different types of FSRs. The proposed architecture is built using a linear and non-linear FSR, making the circuitry further resistant to attacks, and is implemented on Zynq UltraScale+ ZCU104 FPGA device with a clock frequency of 775.2 MHz and the resource utilization is reported. The proposed PRNG is used to encrypt an image from the Fingerprint Verification Contest 2002 (FVC2002) dataset. The strength of the encryption procedure is evaluated on a binary image against various statistical tests. Our implementation improves randomness by 17.4% compared to state-of-the-art implementation, while using a minimal number of resources.
  • Hybrid quantum-classical solution for automated labeling and validation
    Jitesh Lalwani, Dana Linnet, Muthumanimaran Vetrivelan, Kadiyam Hari Venkat, Riyaaz Shaik, Babita Jajodia
    Proceedings of SPIE the International Society for Optical Engineering, 2025
    This paper presents a novel hybrid quantum-classical solution for automating the labeling of hyperspectral data, a critical challenge in dual-use applications across both the civilian and defense sectors. Hyperspectral imaging (HSI) offers unparalleled detail by capturing a wide range of wavelengths, making it invaluable for material identification, environmental monitoring, and intelligence operations. However, the complex and high-dimensional nature of hyperspectral data typically requires manual labeling, a time-consuming and error-prone process. The proposed hybrid solution leverages Quantum Machine Learning (QML), specifically Quantum Support Vector Machines (QSVM), in conjunction with classical statistical techniques to efficiently autolabel hyperspectral data with high accuracy. This research highlights the broad potential of quantum computing to revolutionize data processing for national security, particularly in detecting hidden or camouflaged objects in complex environments. The authors tested the proposed algorithm on IBM quantum hardware and the results are promising. Data validation has been carried out on IBM Brisbane hardware and achieved a classification score of 90%.
  • Approximate Modular Multipliers for R-LWE Cryptosystems on FPGAs and ASICs
    Sahil Maurya, Babita Jajodia
    2024 IEEE Silchar Subsection Conference Silcon 2024, 2024
    This work presents an approximate modular multiplier, termed as AxMM, which includes approximate multiplier (AxMult) and approximate modular reduction (AxMR) using approximate computing (AxC) technique for Ring Learning-with Errors (R-LWE) cryptosystems. This design basically focusses on an area-efficient and power-efficient modular multiplier for R-LWE, a Public Key Encryption (PKE) scheme in Lattice-based Cryptography (LBC), faces challenges in modular polynomial multiplication, particularly for resource-constrained embedded IoT devices. Hardware implementations of the proposed AxMM are done using Virtex-7 Field Programmable Gate Array (FPGA) device. The trade-off between hardware utilization and speed is noted, and the overall performance of the proposed design methods are measured by calculating Area-Time-Product (ATP). Implemented using a Nangate OpenCell 45-nm slow-process Application Specific Inegrated Circuits (ASIC) technology library, the AxMM achieves a comparable power-performance-area (PPA) results in comparable to the existing state-of-the-art R-LWE modular multipliers.
  • FPGA-Based SoC Design with CORDIC-POSIT Arithmetic for Efficient IoT Data Processing
    Suryadev Singh, Babita Jajodia
    2nd IEEE International Conference on Iot Communication and Automation Technology Icicat 2024, 2024
  • Design and Evaluation of FPGA-Optimized Bangladesh Asymmetrical and Symmetrical Five-Term Karatsuba Multipliers
    Raushan Maharana, Monalisa Das, Babita Jajodia
    2024 3rd International Conference on Advancement in Electrical and Electronic Engineering Icaeee 2024, 2024
  • FPGA-Optimized Seven-Term Karatsuba Multipliers for Large Integer Arithmetic
    Raushan Maharana, Arghya Roy, Sourabh Kumar Singh, Monalisa Das, Babita Jajodia
    Proceedings 1st International Conference on Electronics Communication and Signal Processing Icecsp 2024, 2024
  • FPGA-Optimized Eight-Term Karatsuba Multiplications for Large Integer Multiplications
    Shubham Singh, Saubi Patel, Sumit Kumar, Monalisa Das, Babita Jajodia
    2024 International Conference on Recent Innovation in Smart and Sustainable Technology Icrisst 2024, 2024
  • FPGA-Optimized Asymmetrical and Symmetrical Six-Term Karatsuba Multipliers
    Raushan Maharana, Sourabh Kumar Singh, Arghya Roy, Monalisa Das, Babita Jajodia
    Proceedings 1st International Conference on Electronics Communication and Signal Processing Icecsp 2024, 2024
  • Design and Evaluation of FPGA-Optimized Asymmetrical Three-Term Karatsuba Multipliers
    Sumit Kumar, Saubi Patel, Shubham Singh, Monalisa Das, Babita Jajodia
    Proceedings 1st International Conference on Electronics Communication and Signal Processing Icecsp 2024, 2024
  • Design and Evaluation of FPGA-Optimized Symmetrical Three-Term Karatsuba Multipliers
    Sumit Kumar, Saubi Patel, Shubham Singh, Monalisa Das, Babita Jajodia
    2024 International Conference on Recent Innovation in Smart and Sustainable Technology Icrisst 2024, 2024
  • ATP-Optimized Four-Term Karatsuba Multipliers for Large Integer Arithmetic on FPGAs
    Saubi Patel, Shubham Singh, Sumit Kumar, Monalisa Das, Babita Jajodia
    Proceedings 1st International Conference on Electronics Communication and Signal Processing Icecsp 2024, 2024
  • An Eight-Term Karatsuba Multiplier for Cryptographic Hardware Primitives on FPGAs
    Shubham Singh, Saubi Patel, Sumit Kumar, Monalisa Das, Babita Jajodia
    2024 3rd International Conference on Advancement in Electrical and Electronic Engineering Icaeee 2024, 2024
  • FPGA-Optimized Two-Term Karatsuba Multiplications for Large Integer Multiplications
    Sumit Kumar, Saubi Patel, Shubham Singh, Monalisa Das, Babita Jajodia
    Proceedings 11th International Conference on Signal Processing and Integrated Networks Spin 2024, 2024
  • Efficient Earth Observation Satellites Mission Planning with Quantum Algorithm
    Jitesh Lalwani, Dana Linnet, Babita Jajodia, Mandaar B. Pande, Amit Patel, Kshitij Dave, B R Nikilesh
    Tqcebt 2024 2nd IEEE International Conference on Trends in Quantum Computing and Emerging Business Technologies 2024, 2024
  • Hardware Implementation for Determining Perfect and Non-Perfect Square Roots using Dwandwa Yoga on FPGA
    Mansi Thakare, Babita Jajodia
    International Conference on Electrical Computer and Energy Technologies Icecet 2022, 2022
  • Design Automation of Two-Stage Operational Amplifier Using Multi-Objective Genetic Algorithm and SPICE Framework
    Purvi Das, Babita Jajodia
    5th International Conference on Inventive Computation Technologies Icict 2022 Proceedings, 2022
  • Numerical Methods for Solving High-Order Mathematical Problems using Quantum Linear System Algorithm on IBM QISKit Platform
    Simran Jakhodia, Babita Jajodia
    2022 International Conference on Innovative Trends in Information Technology Icitiit 2022, 2022
  • Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA
    Monalisa Das, Babita Jajodia
    Proceedings International Soc Design Conference 2022 Isocc 2022, 2022
  • FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives
    Monalisa Das, Babita Jajodia
    Proceedings International Soc Design Conference 2022 Isocc 2022, 2022
  • Experimental Evaluation of Adder Circuits on IBM QX Hardware
    Divyanshu Singh, Simran Jakhodia, Babita Jajodia
    Lecture Notes in Networks and Systems, 2022
  • Experimental Evaluation of QFT Adders on IBM QX Hardware
    Simran Jakhodia, Divyanshu Singh, Babita Jajodia
    Lecture Notes in Electrical Engineering, 2022
  • Quantum Image Teleportation Protocol (QITP) and Quantum Audio Teleportation Protocol (QATP) by using Quantum Teleportation and Huffman Coding
    Mekala Karthik, Jitesh Lalwani, Babita Jajodia
    2022 International Conference on Trends in Quantum Computing and Emerging Business Technologies Tqcebt 2022, 2022
  • Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA
    Palak Yash, Mansi Thakare, Babita Jajodia
    2022 IEEE 13th Latin American Symposium on Circuits and Systems Lascas 2022, 2022
  • Towards an Optimal Hybrid Algorithm for EV Charging Stations Placement using Quantum Annealing and Genetic Algorithms
    Aman Chandra, Jitesh Lalwani, Babita Jajodia
    2022 International Conference on Trends in Quantum Computing and Emerging Business Technologies Tqcebt 2022, 2022
  • Quantum Text Teleportation Protocol for Secure Text Transfer by using Quantum Teleportation and Huffman Coding
    Mekala Karthik, Jitesh Lalwani, Babita Jajodia
    2022 International Conference on Trends in Quantum Computing and Emerging Business Technologies Tqcebt 2022, 2022
  • HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications
    Divy Pandey, Vishesh Mishra, Saurabh Singh, Sagar Satapathy, Babita Jajodia, Dip Sankar Banerjee
    Proceedings International Symposium on Quality Electronic Design Isqed, 2022
  • EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification
    Saurabh Singh, Vishesh Mishra, Sagar Satapathy, Divy Pandey, Kaustav Goswami, Dip Sankar Banerjee, Babita Jajodia
    Proceedings International Symposium on Quality Electronic Design Isqed, 2022
  • ART-MAC: Approximate Rounding and Truncation based MAC Unit for Fault-Tolerant Applications
    Vishesh Mishra, Divy Pandey, Saurabh Singh, Sagar Satapathy, Kaustav Goswami, Babita Jajodia, Dip Sankar Banerjee
    Proceedings IEEE International Symposium on Circuits and Systems, 2022
  • Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA
    Mansi Thakare, Palak Yash, Debaleena Chakraborty, Babita Jajodia
    Midwest Symposium on Circuits and Systems, 2021
  • Efficient Hardware Implementation of High-Speed Recursive Vedic Squaring Architecture on FPGA
    Jasmine Bajaj, Babita Jajodia
    International Conference on Electrical Computer and Energy Technologies Icecet 2021, 2021
  • Energy-efficient DAC switching technique for single-ended SAR ADCs
    Babita Jajodia, Anil Mahanta, Shaik Rafi Ahamed
    AEU International Journal of Electronics and Communications, 2020
  • IEEE 802.15.6 WBAN Standard Compliant IR-UWB Time-Hopping PPM Transmitter using SRRC signaling pulse
    Babita Jajodia, Anil Mahanta, Shaik Rafi Ahamed
    AEU International Journal of Electronics and Communications, 2020
  • Mixed-signal demodulator for IEEE 802.15.6 IR-UWB WBAN energy detection-based receiver
    Babita Jajodia, Anil Mahanta, Shaik Rafi Ahamed
    Iet Circuits Devices and Systems, 2018
  • Demodulation techniques for IEEE 802.15.6 IR-UWB DBPSK WBAN transceivers
    Babita Jajodia, Rafi Ahamed Shaik, Anil Mahanta
    2015 IEEE International Conference on Smart Instrumentation Measurement and Applications Icsima 2015, 2016
  • PPM demodulation schemes for IEEE 802.15.6 IR-UWB WBAN receivers
    Babita Jajodia, Rafi Ahamed Shaik, Anil Mahanta
    2015 IEEE International Conference on Signal Processing Informatics Communication and Energy Systems Spices 2015, 2015
  • A six-segment SRRC pulse generator for IEEE 802.15.6 WBAN standard
    Shaik Rafi Ahamed, Babita Jajodia, Anil Mahanta
    Bodynets 2014 9th International Conference on Body Area Networks, 2014

RECENT SCHOLAR PUBLICATIONS

  • FPGA Architectures for 32-Point Radix-2 DIT and DIF FFT Using IEEE 754 Half-Precision Floating-Point Arithmetic
    K Shruthi, R Tiwari, B Kanval, B Jajodia
    2026 IEEE Madhya Pradesh Section Conference (MPCON), 744-750 , 2026
    2026
  • Optimized Schoolbook-Based Sub-Multiplication Architecture for Polynomial Multiplication in Large Integer Arithmetic on FPGAs
    M Das, R Maharana, R Tiwari, K Shruthi, V Chaturvedi, GD Gautam, ...
    2026 IEEE Madhya Pradesh Section Conference (MPCON), 760-765 , 2026
    2026
  • Digital Implementation of Cordic-Based Fitzhugh Nagumo Neuron Models on FPGAs
    TD Roy, V Chaturvedi, B Jajodia
    2026 IEEE Madhya Pradesh Section Conference (MPCON), 738-743 , 2026
    2026
  • Hardware Design of Optimized Schoolbook-Based Finite Field Multiplications on FPGAs
    SK Singh, R Maharana, A Roy, K Shruthi, R Tiwari, V Chaturvedi, M Das, ...
    2026 IEEE Madhya Pradesh Section Conference (MPCON), 751-759 , 2026
    2026
  • Interpretable machine learning for diabetes risk prediction: a large-scale analysis of Indian national survey data
    B Barman, HK Choudhury, B Jajodia
    Discover Public Health 22 (1), 832 , 2025
    2025
    Citations: 1
  • Hybrid FSR-Based Pseudo-Random Number Generator on FPGA for Encrypting Biometrics
    K Menon, G Mali, B Jajodia
    2025 37th International Conference on Microelectronics (ICM), 1-5 , 2025
    2025
  • Improved Montgomery Modular Multipliers on FPGAs and ASICs
    A Roy, R Maharana, SK Singh, B Jajodia
    IEEE Embedded Systems Letters , 2025
    2025
  • Division-Free Four-Way Toom-Cook Polynomial Multiplication Architecture for Large Integer Arithmetic on FPGAs and ASICs
    M Das, B Jajodia
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2025
    2025
    Citations: 1
  • Hybrid quantum-classical solution for automated labeling and validation
    J Lalwani, D Linnet, M Vetrivelan, KH Venkat, R Shaik, B Jajodia
    Quantum Information Science, Sensing, and Computation XVII 13451, 51-65 , 2025
    2025
  • ATP-Optimized Implementation of Four-Way Toom-Cook Multiplications on FPGAs for Large Integer Arithmetic
    M Das, B Jajodia
    Circuits, Systems, and Signal Processing 44 (5), 3554-3569 , 2025
    2025
    Citations: 3
  • Floating Point Multipliers on FPGAs
    U Singh, R Mundliya, R Maharana, B Jajodia
    2025 Devices for Integrated Circuit (DevIC), 702-707 , 2025
    2025
    Citations: 1
  • Hybrid recursive Karatsuba multiplications on FPGAs
    M Das, B Jajodia
    IEEE Embedded Systems Letters 17 (4), 240-243 , 2025
    2025
    Citations: 9
  • FPGA-Based SoC Design with CORDIC-POSIT Arithmetic for Efficient IoT Data Processing
    S Singh, B Jajodia
    2024 International Conference on IoT, Communication and Automation … , 2024
    2024
  • Approximate Modular Multipliers for R-LWE Cryptosystems on FPGAs and ASICs
    S Maurya, B Jajodia
    2024 IEEE Silchar Subsection Conference (SILCON 2024), 1-6 , 2024
    2024
  • Area and delay trade-offs in three-way Toom-Cook large integer multipliers implemented on FPGAs
    M Das, B Jajodia
    IEEE Transactions on Circuits and Systems I: Regular Papers 72 (2), 600-609 , 2024
    2024
    Citations: 8
  • ATP-Optimized Four-Term Karatsuba Multipliers for Large Integer Arithmetic on FPGAs
    S Patel, S Singh, S Kumar, M Das, B Jajodia
    2024 First International Conference on Electronics, Communication and Signal … , 2024
    2024
    Citations: 1
  • FPGA-Optimized Seven-Term Karatsuba Multipliers for Large Integer Arithmetic
    R Maharana, A Roy, SK Singh, M Das, B Jajodia
    2024 First International Conference on Electronics, Communication and Signal … , 2024
    2024
    Citations: 2
  • FPGA-Optimized Asymmetrical and Symmetrical Six-Term Karatsuba Multipliers
    R Maharana, SK Singh, A Roy, M Das, B Jajodia
    2024 First International Conference on Electronics, Communication and Signal … , 2024
    2024
    Citations: 1
  • An Eight-Term Karatsuba Multiplier for Cryptographic Hardware Primitives on FPGAs
    S Singh, S Patel, S Kumar, M Das, B Jajodia
    2024 3rd International Conference on Advancement in Electrical and … , 2024
    2024
  • Efficient Earth Observation Satellites Mission Planning with Quantum Algorithm
    J Lalwani, D Linnet, B Jajodia, MB Pande, A Patel, K Dave, BR Nikilesh
    2024 International Conference on Trends in Quantum Computing and Emerging … , 2024
    2024
    Citations: 1

MOST CITED SCHOLAR PUBLICATIONS

  • Design automation of two-stage operational amplifier using multi-objective genetic algorithm and SPICE framework
    P Das, B Jajodia
    2022 International Conference on Inventive Computation Technologies (ICICT … , 2022
    2022
    Citations: 23
  • Hardware design of optimized large integer schoolbook polynomial multiplications on FPGA
    M Das, B Jajodia
    2022 19th International SoC Design Conference (ISOCC), 65-66 , 2022
    2022
    Citations: 20
  • Towards an optimal hybrid algorithm for ev charging stations placement using quantum annealing and genetic algorithms
    A Chandra, J Lalwani, B Jajodia
    2022 International Conference on Trends in Quantum Computing and Emerging … , 2022
    2022
    Citations: 18
  • Energy-efficient DAC switching technique for single-ended SAR ADCs
    B Jajodia, A Mahanta, SR Ahamed
    AEU-International Journal of Electronics and Communications 124, 153334 , 2020
    2020
    Citations: 18
  • Experimental analysis of attacks on rsa & rabin cryptosystems using quantum shor’s algorithm
    R Thombre, B Jajodia
    Proceedings of International Conference on Women Researchers in Electronics … , 2021
    2021
    Citations: 14
  • ART-MAC: Approximate rounding and truncation based MAC unit for fault-tolerant applications
    V Mishra, D Pandey, S Singh, S Satapathy, K Goswami, B Jajodia, ...
    2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1640-1644 , 2022
    2022
    Citations: 11
  • Efcsa: An efficient carry speculative approximate adder with rectification
    S Singh, V Mishra, S Satapathy, D Pandey, K Goswami, DS Banerjee, ...
    2022 23rd International Symposium on Quality Electronic Design (ISQED), 1-7 , 2022
    2022
    Citations: 11
  • IEEE 802.15. 6 WBAN standard compliant IR-UWB time-hopping PPM transmitter using SRRC signaling pulse
    B Jajodia, A Mahanta, SR Ahamed
    AEU-International Journal of Electronics and Communications 117, 153119 , 2020
    2020
    Citations: 10
  • Hybrid recursive Karatsuba multiplications on FPGAs
    M Das, B Jajodia
    IEEE Embedded Systems Letters 17 (4), 240-243 , 2025
    2025
    Citations: 9
  • HPAM: An 8-bit high-performance approximate multiplier design for error resilient applications
    D Pandey, V Mishra, S Singh, S Satapathy, B Jajodia, DS Banerjee
    2022 23rd International Symposium on Quality Electronic Design (ISQED), 1-5 , 2022
    2022
    Citations: 9
  • Area and delay trade-offs in three-way Toom-Cook large integer multipliers implemented on FPGAs
    M Das, B Jajodia
    IEEE Transactions on Circuits and Systems I: Regular Papers 72 (2), 600-609 , 2024
    2024
    Citations: 8
  • FPGA implementation of hybrid Karatsuba multiplications for NIST post-quantum cryptographic hardware primitives
    M Das, B Jajodia
    2022 19th International SoC Design Conference (ISOCC), 81-82 , 2022
    2022
    Citations: 7
  • Quantum image teleportation protocol (QITP) and quantum audio teleportation protocol (QATP) by using quantum teleportation and huffman coding
    M Karthik, J Lalwani, B Jajodia
    2022 International Conference on Trends in Quantum Computing and Emerging … , 2022
    2022
    Citations: 6
  • Quantum Text Teleportation Protocol for Secure Text Transfer by using Quantum Teleportation and Huffman Coding
    M Karthik, J Lalwani, B Jajodia
    2022 International Conference on Trends in Quantum Computing and Emerging … , 2022
    2022
    Citations: 5
  • Efficient hardware implementation of cube architecture using Yavadunam Sutra on FPGA
    M Thakare, P Yash, D Chakraborty, B Jajodia
    2021 IEEE international midwest symposium on circuits and systems (MWSCAS … , 2021
    2021
    Citations: 5
  • Hardware implementation for determining perfect and non-perfect square roots using dwandwa yoga on fpga
    M Thakare, B Jajodia
    2022 international conference on electrical, computer and energy … , 2022
    2022
    Citations: 4
  • Experimental evaluation of adder circuits on IBM QX Hardware
    D Singh, S Jakhodia, B Jajodia
    Inventive Computation and Information Technologies: Proceedings of ICICIT … , 2022
    2022
    Citations: 4
  • Demodulation techniques for IEEE 802.15. 6 IR-UWB DBPSK WBAN transceivers
    B Jajodia, RA Shaik, A Mahanta
    2015 IEEE 3rd International Conference on Smart Instrumentation, Measurement … , 2015
    2015
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