Arish Sateesan

@rwth-aachen.de

Postdoctoral researcher, Electrical Engineering and Information Technology
RWTH Aachen University

Arish Sateesan


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https://researchid.co/arishs

RESEARCH, TEACHING, or OTHER INTERESTS

Electrical and Electronic Engineering, Hardware and Architecture, Computer Networks and Communications, Artificial Intelligence
18

Scopus Publications

Scopus Publications

  • Breaking the Scalability Barrier of Content Addressable Memories: A Probabilistic Alternative for Large-Key Associative Search
    Arish Sateesan, Jo Vliegen, Nele Mentens
    ACM Transactions on Reconfigurable Technology and Systems, 2026
    Content Addressable Memories (CAMs) offer high-speed, deterministic lookups but face significant scalability challenges with large input keys ( \( > \) 100 bits), leading to excessive power, silicon area, and memory costs. This article introduces Probabilistic CAM (P-CAM), a novel architecture designed to overcome these limitations by trading strict determinism for memory efficiency and scalability. P-CAM compresses high-dimensional inputs into fixed-size fingerprints using hashing, making memory requirements independent of key length. P-CAM preserves the constant-time lookup advantage of CAMs, while supporting applications with large keys, such as networking, bioinformatics, and machine learning, where conventional CAMs are impractical. FPGA implementation on Xilinx UltraScale+ devices shows that P-CAM maintains constant query latency and delivers 15 \(\times\) improvement in resource efficiency when handling 384-bit keys, compared to state-of-the-art deterministic CAMs designed for narrower inputs. Although P-CAM’s probabilistic nature introduces a small, controllable false-positive rate, it can be configured for fully deterministic operation under specific constraints. To the best of our knowledge, P-CAM is the first CAM architecture to employ a fingerprint-based probabilistic data structure as the primary storage mechanism for associative lookup, distinguishing it from prior probabilistic approaches that are limited to set membership checks, offering a robust and scalable alternative for modern data-intensive systems.
  • FPGA-Powered Environment Awareness via Quantized Neural Networks for LiDAR-Aided mm-Wave Beam Prediction
    Arish Sateesan, Ljiljana Simić
    2025 IEEE International Conference on Machine Learning for Communication and Networking Icmlcn 2025, 2025
    Environment awareness can be highly beneficial for robust and agile beam prediction, particularly for beyond-5G millimeter-wave (mm-wave) networks. While machine learning (ML) algorithms have shown potential in leveraging external sensor data, such as LiDAR, radar, and cameras, to enhance beam prediction, existing solutions often rely on simulations or offline data processing, limiting their applicability in real-world deployments. Real-world deployment of such solutions requires low-latency ML inference tailored to resource-constrained hardware platforms but remains challenging due to the computational complexity and latency demands of ML models. This paper addresses these challenges by implementing real-time ML inference in hardware focusing on environment awareness using LiDAR data. We present an FPGA-based implementation of Quantized Neural Networks (QNNs) optimized for real-time LiDAR-aided beam prediction in beyond-5G mm-wave networks. Evaluations on the ZCU104 FPGA platform using real-world datasets demonstrate inference latencies in the tens to hundreds of microseconds, achieving comparable accuracy to state-of-the-art methods with only 2-bit weights and activations. Our results underline the effectiveness of the QNNs in achieving high accuracy, low latency, and hardware resource efficiency for real-world mm-wave applications.
  • FLARE: An FPGA-Based Universal Large Flow Detection Engine
    Arish Sateesan, Jo Vliegen, Nele Mentens
    Lecture Notes in Computer Science, 2025
  • ITERATOR: Interruptible Remote Attestation Through Cuckoo Filters
    Nicoló Sponziello, Arish Sateesan, Md Masoom Rabbani, Nele Mentens, Nicola Dragoni, Edlira Dushku
    IEEE Internet of Things Journal, 2025
    Remote attestation (RA) is emerging as a promising security mechanism that establishes trust in IoT devices by detecting the malware presence. Typically, RA consists of computing a hash over the device’s memory and is executed as an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">atomic</i> procedure to guarantee the reliability of the attestation evidence. However, in real-world situations, such as those involving real-time systems, energy-harvesting devices, or mission-critical operations, the IoT device may not be able to complete the attestation procedure due to various factors like task scheduling, limited battery life, or higher priority tasks. In such scenarios where flexibility, adaptability, and security are paramount, enabling <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">interruptibility</i> of RA is crucial. This paper presents a novel approach called ITERATOR which leverages hash-based storage to enable interruptible RA without any additional hardware requirements. Our proposal transforms the device attestation procedure from the traditional approach of memory hash computation to a lookup operation in a hash-based storage, namely, Cuckoo filter. The ITERATOR protocol divides the device’s memory into blocks associated with a Cuckoo filter bucket. This approach allows the device to perform RA in multiple rounds, ensuring secure interruptible attestation. We perform software simulations of ITERATOR, demonstrating its high effectiveness in detecting the malware presence. Due to its interruptible design, ITERATOR cannot guarantee 100% detection in a single attestation round; however, repeated rounds make long-term evasion by malware highly unlikely. In particular, the experiments showed that the probability of evading the detection ranges between 37% and less than 1%, depending on the protocol configuration. Moreover, we validate ITERATOR’s efficiency through two hardware proof-of-concept implementations that rely on ESP32 and FPGA platforms. The FPGA implementation shows the high efficiency of the protocol, with 34.3ns to attest a single memory block.
  • A Genetic Programming approach for hardware-oriented hash functions for network security applications
    Mujtaba Hassan, Arish Sateesan, Jo Vliegen, Stjepan Picek, Nele Mentens
    Applied Soft Computing, 2024
  • SPArch: A Hardware-oriented Sketch-based Architecture for High-speed Network Flow Measurements
    Arish Sateesan, Jo Vliegen, Simon Scherrer, Hsu-Chun Hsiao, Adrian Perrig, Nele Mentens
    ACM Transactions on Privacy and Security, 2024
    Network flow measurement is an integral part of modern high-speed applications for network security and data-stream processing. However, processing at line rate while maintaining the required data structure within the on-chip memory of the hardware platform is a challenging task for measurement algorithms, especially when accuracy is of primary importance, such as in network security applications. Most of the existing measurement algorithms are no exception to such issues when deployed in high-speed networking environments and are also not tailored for efficient hardware implementation. Sketch-based measurement algorithms minimize the memory requirement and are suitable for high-speed networks but possess a low memory-accuracy trade-off and lack the versatility of individual flow mapping. To address these challenges, we present a hardware-friendly data structure named Sketch-based Pseudo-associative array Architecture (SPArch). SPArch is highly accurate and extremely memory-efficient, making it suitable for network flow measurement and security applications. The parallelism in SPArch ensures minimal and constant memory access cycles. Unlike other sketch architectures, SPArch provides the functionality of individual flow mapping similar to associative arrays, and the optimized version of SPArch allows the organization of counters in multiple buckets based on the flow sizes. An in-depth analysis of SPArch is carried out in this article and implemented SPArch on the Alveo data center accelerator card, demonstrating its suitability for high-speed networks.
  • Optimized algorithms and architectures for fast non-cryptographic hash functions in hardware
    Arish Sateesan, Jelle Biesmans, Thomas Claesen, Jo Vliegen, Nele Mentens
    Microprocessors and Microsystems, 2023
  • Evolving Non-cryptographic Hash Functions Using Genetic Programming for High-speed Lookups in Network Security Applications
    Mujtaba Hassan, Arish Sateesan, Jo Vliegen, Stjepan Picek, Nele Mentens
    Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 2023
  • ALBUS: A Probabilistic Monitoring Algorithm to Counter Burst-Flood Attacks
    Simon Scherrer, Jo Vliegen, Arish Sateesan, Hsu-Chun Hsiao, Nele Mentens, Adrian Perrig
    Proceedings of the IEEE Symposium on Reliable Distributed Systems, 2023
    Modern DDoS defense systems rely on probabilistic monitoring algorithms to identify flows that exceed a volume threshold and should thus be penalized. Commonly, classic sketch algorithms are considered sufficiently accurate for usage in DDoS defense. However, as we show in this paper, these algorithms achieve poor detection accuracy under burst-flood attacks, i.e., volumetric DDoS attacks composed of a swarm of medium-rate sub-second traffic bursts. Under this challenging attack pattern, traditional sketch algorithms can only detect a high share of the attack bursts by incurring a large number of false positives. In this paper, we present ALBUS, a probabilistic monitoring algorithm that overcomes the inherent limitations of previous schemes: ALBUS is highly effective at detecting large bursts while reporting no legitimate flows, and therefore improves on prior work regarding both recall and precision. Besides improving accuracy, ALBUS scales to high traffic rates, which we demonstrate with an FPGA implementation, and is suitable for programmable switches, which we showcase with a P4 implementation.
  • Hardware-oriented optimization of Bloom filter algorithms and architectures for ultra-high-speed lookups in network applications
    Arish Sateesan, Jo Vliegen, Joan Daemen, Nele Mentens
    Microprocessors and Microsystems, 2022
  • An Analysis of the Hardware-Friendliness of AMQ Data Structures for Network Security
    Arish Sateesan, Jo Vliegen, Nele Mentens
    Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 2022
  • SoK - Network Intrusion Detection on FPGA
    Laurens Le Jeune, Arish Sateesan, Md Masoom Rabbani, Toon Goedemé, Jo Vliegen, Nele Mentens
    Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 2022
  • A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs
    Arish Sateesan, Sharad Sinha, Smitha K. G., A. P. Vinod
    Neural Processing Letters, 2021
  • Novel Non-cryptographic Hash Functions for Networking and Security Applications on FPGA
    Thomas Claesen, Arish Sateesan, Jo Vliegen, Nele Mentens
    Proceedings 2021 24th Euromicro Conference on Digital System Design Dsd 2021, 2021
  • Speed records in network flow measurement on FPGA
    Arish Sateesan, Jo Vliegen, Simon Scherrer, Hsu-Chun Hsiao, Adrian Perrig, Nele Mentens
    Proceedings 2021 31st International Conference on Field Programmable Logic and Applications Fpl 2021, 2021
  • Low-Rate Overuse Flow Tracer (LOFT): An Efficient and Scalable Algorithm for Detecting Overuse Flows
    Simon Scherrer, Che-Yu Wu, Yu-Hsi Chiang, Benjamin Rothenberger, Daniele E. Asoni, Arish Sateesan, Jo Vliegen, Nele Mentens, Hsu-Chun Hsiao, Adrian Perrig
    Proceedings of the IEEE Symposium on Reliable Distributed Systems, 2021
  • DASH: Design Automation for Synthesis and Hardware Generation for CNN
    Arish Sateesan, Sharad Sinha, Smitha K G
    Proceedings 2020 International Conference on Field Programmable Technology Icfpt 2020, 2020
  • Novel Bloom filter algorithms and architectures for ultra-high-speed network security applications
    Arish Sateesan, Jo Vliegen, Joan Daemen, Nele Mentens
    Proceedings Euromicro Conference on Digital System Design Dsd 2020, 2020